EXAMPLE START-UP ROUTINE 
There are certain sequences that should be followed to ensure 
reliable start-up of the AD9122. This section shows an example 
start-up routine assuming the configuration detailed in the 
following section. 
Device Configuration 
The following device configuration is used for this example: 
fDATA = 122.88MSPS 
Interpolation = 4x, using HB1=10 and 
HB2=010010 
Input data = Baseband data 
fOUT = 140MHz 
fREFCLK = 122.88MHz 
PLL = Enabled 
Fine NCO = Enabled 
Inverse SINC Filter = Enabled 
Synchronization = Enabled 
Silicon Revision = R2 
 
Derived PLL Settings 
The following PLL settings can be derived from the device 
configuration: 
fDACCLK=fDATA*Interpolation=491.52MHz 
fVCO = 4*fDACCLK=1966.08MHz (1GHz < fVCO < 2GHz) 
N1=fDACCLK/fREFCLK=4 
N2=fVCO/fDACCLK=4 
 
Derived NCO Settings 
The following NCO settings can be derived from the device 
configuration: 
fNCO = 2 * fDATA 
fCARRIER=fOUT-fMODHB1=140-122.88=17.12MHz 
FTW=17.12/(2*122.88)*2^32=0x11D55555 
 
Start-Up Sequence 
The following sequences the power clock and register write 
sequencing for reliable device start-up: 
Power up Device (no specific power supply 
sequence is required) 
Apply stable REFCLK input signal. 
Apply stable DCI input signal. 
Issue H/W RESET (Optional) 
 
Device Configuration Register Write Sequence: 
 
0x00 ? 0x20  /* Issue Software Reset */ 
0x00 ? 0x00 
 
0x0B ? 0x20  /* Start PLL */ 
0x0C ? 0xE1 
0x0D ? 0xD9 
0x0A ? 0xCF 
0x0A ? 0xA0 
    /* ??Verify PLL is Locked?? */ 
 
Read 0x0E, Expect bit 7 = 0, bit 6 = 1 
Read 0x06, Expect 0x5C 
 
0x10 ? 0x48  /* Choose Data Rate Mode */ 
0x17 ? 0x04  /* Issue Software FIFO Reset */ 
0x18 ? 0x02 
0x18 ? 0x00 
/* ??Verify FIFO Reset?? */ 
 
Read 0x18, Expect 0x05 
Read 0x19, Expect 0x07 
 
0x1B ? 0x84  /* Configure Interpolation Filters */ 
0x1C ? 0x04 
0x1D ? 0x24 
 
0x1E ? 0x01  /* Configure NCO */ 
0x30 ? 0x55 
0x31 ? 0x55 
0x32 ? 0xD5 
0x33 ? 0x11 
0x36 ? 0x01  /* Update Frequency Tuning Word */ 
0x36 ? 0x00 