Loading plugins phase: Elapsed time ==> 0s.436ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -d CY8C5888LTI-LP097 -s C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 3s.494ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.109ms
<CYPRESSTAG name="Synthesis results...">

     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp Verilog Synthesis Compiler: Version 6.3 IR 41
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  CE195352_PSoC_5LP_FATFS.v
Program  :   C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -dcpsoc3 CE195352_PSoC_5LP_FATFS.v -verilog
======================================================================

======================================================================
Compiling:  CE195352_PSoC_5LP_FATFS.v
Program  :   C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -dcpsoc3 CE195352_PSoC_5LP_FATFS.v -verilog
======================================================================

======================================================================
Compiling:  CE195352_PSoC_5LP_FATFS.v
Program  :   vlogfe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -dcpsoc3 -verilog CE195352_PSoC_5LP_FATFS.v
======================================================================

vlogfe V6.3 IR 41:  Verilog parser
Sat Apr 28 17:19:42 2018


======================================================================
Compiling:  CE195352_PSoC_5LP_FATFS.v
Program  :   vpp
Options  :    -yv2 -q10 CE195352_PSoC_5LP_FATFS.v
======================================================================

vpp V6.3 IR 41:  Verilog Pre-Processor
Sat Apr 28 17:19:42 2018

Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\not_v1_0\not_v1_0.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v'
Flattening file 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'

vpp:  No errors.

Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'CE195352_PSoC_5LP_FATFS.ctl'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.

vlogfe:  No errors.


======================================================================
Compiling:  CE195352_PSoC_5LP_FATFS.v
Program  :   tovif
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -dcpsoc3 -verilog CE195352_PSoC_5LP_FATFS.v
======================================================================

tovif V6.3 IR 41:  High-level synthesis
Sat Apr 28 17:19:43 2018

Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\codegentemp\CE195352_PSoC_5LP_FATFS.ctl'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\codegentemp\CE195352_PSoC_5LP_FATFS.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\not_v1_0\not_v1_0.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.

tovif:  No errors.


======================================================================
Compiling:  CE195352_PSoC_5LP_FATFS.v
Program  :   topld
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -dcpsoc3 -verilog CE195352_PSoC_5LP_FATFS.v
======================================================================

topld V6.3 IR 41:  Synthesis and optimization
Sat Apr 28 17:19:44 2018

Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\codegentemp\CE195352_PSoC_5LP_FATFS.ctl'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\codegentemp\CE195352_PSoC_5LP_FATFS.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\not_v1_0\not_v1_0.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\B_SPI_Master_v2_40\B_SPI_Master_v2_40.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cy_psoc3_inc.v'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3pkg.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\cy_psoc3.vif'.
Linking 'C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	Net_276
	Net_273
	\PWM_1:Net_114\
	\emFile_1:SPI0:BSPIM:mosi_after_ld\
	\emFile_1:SPI0:BSPIM:so_send\
	\emFile_1:SPI0:BSPIM:mosi_cpha_1\
	\emFile_1:SPI0:BSPIM:pre_mosi\
	\emFile_1:SPI0:BSPIM:dpcounter_zero\
	\emFile_1:SPI0:BSPIM:control_7\
	\emFile_1:SPI0:BSPIM:control_6\
	\emFile_1:SPI0:BSPIM:control_5\
	\emFile_1:SPI0:BSPIM:control_4\
	\emFile_1:SPI0:BSPIM:control_3\
	\emFile_1:SPI0:BSPIM:control_2\
	\emFile_1:SPI0:BSPIM:control_1\
	\emFile_1:SPI0:BSPIM:control_0\
	\emFile_1:SPI0:Net_253\
	\emFile_1:Net_2\


Deleted 18 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing Net_136 to zero
Aliasing tmpOE__PWM_Out_1_net_0 to \PWM_1:Net_113\
Aliasing one to \PWM_1:Net_113\
Aliasing tmpOE__Kill_Switch_net_0 to \PWM_1:Net_113\
Aliasing \emFile_1:SPI0:BSPIM:pol_supprt\ to zero
Aliasing \emFile_1:SPI0:BSPIM:tx_status_3\ to \emFile_1:SPI0:BSPIM:load_rx_data\
Aliasing \emFile_1:SPI0:BSPIM:tx_status_6\ to zero
Aliasing \emFile_1:SPI0:BSPIM:tx_status_5\ to zero
Aliasing \emFile_1:SPI0:BSPIM:rx_status_3\ to zero
Aliasing \emFile_1:SPI0:BSPIM:rx_status_2\ to zero
Aliasing \emFile_1:SPI0:BSPIM:rx_status_1\ to zero
Aliasing \emFile_1:SPI0:BSPIM:rx_status_0\ to zero
Aliasing \emFile_1:SPI0:Net_274\ to zero
Aliasing \emFile_1:tmpOE__mosi0_net_0\ to \PWM_1:Net_113\
Aliasing \emFile_1:tmpOE__miso0_net_0\ to \PWM_1:Net_113\
Aliasing \emFile_1:tmpOE__sclk0_net_0\ to \PWM_1:Net_113\
Aliasing \emFile_1:tmpOE__SPI0_CS_net_0\ to \PWM_1:Net_113\
Aliasing \emFile_1:SPI0:BSPIM:so_send_reg\\D\ to zero
Aliasing \emFile_1:SPI0:BSPIM:dpcounter_one_reg\\D\ to \emFile_1:SPI0:BSPIM:load_rx_data\
Removing Lhs of wire \PWM_1:Net_107\[3] = Net_267[13]
Removing Lhs of wire Net_136[6] = zero[5]
Removing Rhs of wire Net_254[10] = \PWM_1:Net_57\[8]
Removing Rhs of wire tmpOE__PWM_Out_1_net_0[16] = \PWM_1:Net_113\[4]
Removing Lhs of wire one[21] = tmpOE__PWM_Out_1_net_0[16]
Removing Lhs of wire tmpOE__Kill_Switch_net_0[24] = tmpOE__PWM_Out_1_net_0[16]
Removing Lhs of wire \emFile_1:SPI0:Net_276\[38] = \emFile_1:Net_19\[39]
Removing Rhs of wire \emFile_1:SPI0:BSPIM:load_rx_data\[42] = \emFile_1:SPI0:BSPIM:dpcounter_one\[43]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:pol_supprt\[44] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:miso_to_dp\[45] = \emFile_1:SPI0:Net_244\[46]
Removing Lhs of wire \emFile_1:SPI0:Net_244\[46] = \emFile_1:Net_16\[139]
Removing Rhs of wire \emFile_1:Net_10\[50] = \emFile_1:SPI0:BSPIM:mosi_fin\[51]
Removing Rhs of wire \emFile_1:Net_10\[50] = \emFile_1:SPI0:BSPIM:mosi_cpha_0\[52]
Removing Rhs of wire \emFile_1:SPI0:BSPIM:tx_status_1\[73] = \emFile_1:SPI0:BSPIM:dpMOSI_fifo_empty\[74]
Removing Rhs of wire \emFile_1:SPI0:BSPIM:tx_status_2\[75] = \emFile_1:SPI0:BSPIM:dpMOSI_fifo_not_full\[76]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:tx_status_3\[77] = \emFile_1:SPI0:BSPIM:load_rx_data\[42]
Removing Rhs of wire \emFile_1:SPI0:BSPIM:rx_status_4\[79] = \emFile_1:SPI0:BSPIM:dpMISO_fifo_full\[80]
Removing Rhs of wire \emFile_1:SPI0:BSPIM:rx_status_5\[81] = \emFile_1:SPI0:BSPIM:dpMISO_fifo_not_empty\[82]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:tx_status_6\[84] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:tx_status_5\[85] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:rx_status_3\[86] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:rx_status_2\[87] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:rx_status_1\[88] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:rx_status_0\[89] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:Net_273\[99] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:Net_274\[140] = zero[5]
Removing Lhs of wire \emFile_1:tmpOE__mosi0_net_0\[142] = tmpOE__PWM_Out_1_net_0[16]
Removing Lhs of wire \emFile_1:tmpOE__miso0_net_0\[149] = tmpOE__PWM_Out_1_net_0[16]
Removing Lhs of wire \emFile_1:tmpOE__sclk0_net_0\[155] = tmpOE__PWM_Out_1_net_0[16]
Removing Lhs of wire \emFile_1:tmpOE__SPI0_CS_net_0\[161] = tmpOE__PWM_Out_1_net_0[16]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:so_send_reg\\D\[166] = zero[5]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:mosi_reg\\D\[173] = \emFile_1:SPI0:BSPIM:mosi_pre_reg\[66]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:dpcounter_one_reg\\D\[175] = \emFile_1:SPI0:BSPIM:load_rx_data\[42]
Removing Lhs of wire \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\\D\[176] = \emFile_1:SPI0:BSPIM:mosi_from_dp\[56]

------------------------------------------------------
Aliased 0 equations, 34 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

Substituting virtuals - pass 1:

Note:  Expanding virtual equation for 'zero' (cost = 0):
zero <=  ('0') ;

Note:  Expanding virtual equation for '\emFile_1:SPI0:BSPIM:load_rx_data\' (cost = 1):
\emFile_1:SPI0:BSPIM:load_rx_data\ <= ((not \emFile_1:SPI0:BSPIM:count_4\ and not \emFile_1:SPI0:BSPIM:count_3\ and not \emFile_1:SPI0:BSPIM:count_2\ and not \emFile_1:SPI0:BSPIM:count_1\ and \emFile_1:SPI0:BSPIM:count_0\));


Substituting virtuals - pass 2:


----------------------------------------------------------
Circuit simplification results:

	Expanded 2 signals.
	Turned 0 signals into soft nodes.
	Maximum default expansion cost was set at 3.
----------------------------------------------------------

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

Last attempt to remove unused logic - pass 1:


Last attempt to remove unused logic - pass 2:


topld:  No errors.

CYPRESS_DIR    : C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp
Warp Program   : C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe
Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -dcpsoc3 CE195352_PSoC_5LP_FATFS.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 3s.634ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Saturday, 28 April 2018 17:19:45
Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Sujoy\Dropbox\PSOC\Workspace02\CE195352_PSoC_5LP_Blinking_LED\CE195352_PSoC_5LP_FATFS.cydsn\CE195352_PSoC_5LP_FATFS.cyprj -d CY8C5888LTI-LP097 CE195352_PSoC_5LP_FATFS.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.046ms
</CYPRESSTAG>
<CYPRESSTAG name="Tech Mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
    Converted constant MacroCell: \emFile_1:SPI0:BSPIM:so_send_reg\ from registered to combinatorial
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
    Digital Clock 0: Automatic-assigning  clock 'emFile_1_Clock_1'. Fanout=1, Signal=\emFile_1:Net_19\
    Digital Clock 1: Automatic-assigning  clock 'clock_1'. Fanout=1, Signal=Net_134
</CYPRESSTAG>

Removing unused cells resulting from optimization
Done removing unused cells.
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
    UDB Clk/Enable \emFile_1:SPI0:BSPIM:ClkEn\: with output requested to be synchronous
        ClockIn: emFile_1_Clock_1 was determined to be a global clock that is synchronous to BUS_CLK
        EnableIn: Constant 1 was determined to be synchronous to ClockIn
        ClockOut: emFile_1_Clock_1, EnableOut: Constant 1
</CYPRESSTAG>

Removing unused cells resulting from optimization
Done removing unused cells.
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">

------------------------------------------------------------
Design Equations
------------------------------------------------------------
    <CYPRESSTAG name="Pin listing">

    ------------------------------------------------------------
    Pin listing
    ------------------------------------------------------------

    Pin : Name = PWM_Out_1(0)
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => PWM_Out_1(0)__PA ,
            pin_input => Net_254 ,
            annotation => Net_260 ,
            pad => PWM_Out_1(0)_PAD );
        Properties:
        {
        }

    Pin : Name = Kill_Switch(0)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: RES_PULL_UP
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => Kill_Switch(0)__PA ,
            fb => Net_268 ,
            annotation => Net_264 ,
            pad => Kill_Switch(0)_PAD );
        Properties:
        {
        }

    Pin : Name = \emFile_1:mosi0(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \emFile_1:mosi0(0)\__PA ,
            pin_input => \emFile_1:Net_10\ ,
            pad => \emFile_1:mosi0(0)_PAD\ );
        Properties:
        {
        }

    Pin : Name = \emFile_1:miso0(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: NOSYNC
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_DIGITAL
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \emFile_1:miso0(0)\__PA ,
            fb => \emFile_1:Net_16\ ,
            pad => \emFile_1:miso0(0)_PAD\ );
        Properties:
        {
        }

    Pin : Name = \emFile_1:sclk0(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \emFile_1:sclk0(0)\__PA ,
            pin_input => \emFile_1:Net_22\ ,
            pad => \emFile_1:sclk0(0)_PAD\ );
        Properties:
        {
        }

    Pin : Name = \emFile_1:SPI0_CS(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: CMOS_OUT
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \emFile_1:SPI0_CS(0)\__PA ,
            pad => \emFile_1:SPI0_CS(0)_PAD\ );
        Properties:
        {
        }
    </CYPRESSTAG>
    <CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">

    ------------------------------------------------------------
    Macrocell listing
    ------------------------------------------------------------

    MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_pre_reg_split\, Mode=(Combinatorial)
        Total # of inputs        : 11
        Total # of product terms : 8
            Clock Enable: True
        Main Equation            : 8 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_4\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_3\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_2\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_1\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              !\emFile_1:SPI0:BSPIM:count_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_pre_reg\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              \emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_pre_reg\
            + \emFile_1:SPI0:BSPIM:state_1\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ (fanout=1)

    MacroCell: Name=Net_267, Mode=(Combinatorial)
        Total # of inputs        : 1
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !Net_268
        );
        Output = Net_267 (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:load_rx_data\, Mode=(Combinatorial)
        Total # of inputs        : 5
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              \emFile_1:SPI0:BSPIM:count_0\
        );
        Output = \emFile_1:SPI0:BSPIM:load_rx_data\ (fanout=2)

    MacroCell: Name=\emFile_1:Net_10\, Mode=(Combinatorial)
        Total # of inputs        : 5
        Total # of product terms : 3
            Clock Enable: True
        Main Equation            : 3 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:Net_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:Net_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
            + !\emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:Net_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
        );
        Output = \emFile_1:Net_10\ (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:tx_status_0\, Mode=(Combinatorial)
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:tx_status_0\ (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:tx_status_4\, Mode=(Combinatorial)
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:tx_status_4\ (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:rx_status_6\, Mode=(Combinatorial)
        Total # of inputs        : 6
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              \emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:rx_status_4\
        );
        Output = \emFile_1:SPI0:BSPIM:rx_status_6\ (fanout=1)

    MacroCell: Name=__ONE__, Mode=(Combinatorial)
        Total # of inputs        : 0
        Total # of product terms : 0
            Clock Enable: True
        Main Equation            : 0 pterms
        !(
            0
        );
        Output = __ONE__ (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\, Mode=(Combinatorial)
        Total # of inputs        : 10
        Total # of product terms : 6
            Clock Enable: True
        Main Equation            : 6 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
            + !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_0\
            + !\emFile_1:SPI0:BSPIM:state_2\ * 
              !\emFile_1:SPI0:BSPIM:mosi_pre_reg\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * 
              !\emFile_1:SPI0:BSPIM:mosi_from_dp\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:state_2\, Mode=(D-Register)
        Total # of inputs        : 10
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_1\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * \emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
            + \emFile_1:SPI0:BSPIM:state_1\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              \emFile_1:SPI0:BSPIM:count_2\ * \emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:tx_status_1\
        );
        Output = \emFile_1:SPI0:BSPIM:state_2\ (fanout=15)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:state_1\, Mode=(D-Register)
        Total # of inputs        : 10
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              \emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * \emFile_1:SPI0:BSPIM:count_2\ * 
              \emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:tx_status_1\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:state_1\ (fanout=15)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:state_0\, Mode=(T-Register)
        Total # of inputs        : 10
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:tx_status_1\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * \emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
        );
        Output = \emFile_1:SPI0:BSPIM:state_0\ (fanout=15)

    MacroCell: Name=\emFile_1:Net_1\, Mode=(D-Register)
        Total # of inputs        : 4
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:Net_1\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:Net_1\
        );
        Output = \emFile_1:Net_1\ (fanout=2)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_hs_reg\, Mode=(D-Register)
        Total # of inputs        : 6
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\
            + !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
            + !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_hs_reg\ (fanout=2)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_pre_reg\, Mode=(D-Register)
        Total # of inputs        : 2
        Total # of product terms : 1
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              !\emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ * 
              !\emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_pre_reg\ (fanout=2)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:load_cond\, Mode=(T-Register)
        Total # of inputs        : 9
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:load_cond\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:load_cond\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:load_cond\
            + \emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:load_cond\
        );
        Output = \emFile_1:SPI0:BSPIM:load_cond\ (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_from_dp_reg\, Mode=(D-Register)
        Total # of inputs        : 1
        Total # of product terms : 1
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              \emFile_1:SPI0:BSPIM:mosi_from_dp\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\ (fanout=1)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:ld_ident\, Mode=(T-Register)
        Total # of inputs        : 9
        Total # of product terms : 2
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * \emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:ld_ident\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
        );
        Output = \emFile_1:SPI0:BSPIM:ld_ident\ (fanout=6)

    MacroCell: Name=\emFile_1:SPI0:BSPIM:cnt_enable\, Mode=(T-Register)
        Total # of inputs        : 4
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:cnt_enable\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:cnt_enable\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:cnt_enable\
        );
        Output = \emFile_1:SPI0:BSPIM:cnt_enable\ (fanout=2)

    MacroCell: Name=\emFile_1:Net_22\, Mode=(D-Register)
        Total # of inputs        : 4
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        (
              \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:Net_22\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:Net_22\ (fanout=2)
    </CYPRESSTAG>
    <CYPRESSTAG name="Datapath listing">

    ------------------------------------------------------------
    Datapath listing
    ------------------------------------------------------------

    datapathcell: Name =\emFile_1:SPI0:BSPIM:sR8:Dp:u0\
        PORT MAP (
            clock => \emFile_1:Net_19\ ,
            cs_addr_2 => \emFile_1:SPI0:BSPIM:state_2\ ,
            cs_addr_1 => \emFile_1:SPI0:BSPIM:state_1\ ,
            cs_addr_0 => \emFile_1:SPI0:BSPIM:state_0\ ,
            route_si => \emFile_1:Net_16\ ,
            f1_load => \emFile_1:SPI0:BSPIM:load_rx_data\ ,
            so_comb => \emFile_1:SPI0:BSPIM:mosi_from_dp\ ,
            f0_bus_stat_comb => \emFile_1:SPI0:BSPIM:tx_status_2\ ,
            f0_blk_stat_comb => \emFile_1:SPI0:BSPIM:tx_status_1\ ,
            f1_bus_stat_comb => \emFile_1:SPI0:BSPIM:rx_status_5\ ,
            f1_blk_stat_comb => \emFile_1:SPI0:BSPIM:rx_status_4\ );
        Properties:
        {
            a0_init = "00000000"
            a1_init = "00000000"
            ce0_sync = 1
            ce1_sync = 1
            cl0_sync = 1
            cl1_sync = 1
            cmsb_sync = 1
            co_msb_sync = 1
            cy_dpconfig = "0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001000111100000000000000000100"
            d0_init = "00000000"
            d1_init = "00000000"
            f0_blk_sync = 1
            f0_bus_sync = 1
            f1_blk_sync = 1
            f1_bus_sync = 1
            ff0_sync = 1
            ff1_sync = 1
            ov_msb_sync = 1
            so_sync = 1
            z0_sync = 1
            z1_sync = 1
        }
        Clock Polarity: Active High
        Clock Enable: True
    </CYPRESSTAG>
    <CYPRESSTAG name="Status register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="StatusI register listing">

    ------------------------------------------------------------
    StatusI register listing
    ------------------------------------------------------------

    statusicell: Name =\emFile_1:SPI0:BSPIM:TxStsReg\
        PORT MAP (
            clock => \emFile_1:Net_19\ ,
            status_4 => \emFile_1:SPI0:BSPIM:tx_status_4\ ,
            status_3 => \emFile_1:SPI0:BSPIM:load_rx_data\ ,
            status_2 => \emFile_1:SPI0:BSPIM:tx_status_2\ ,
            status_1 => \emFile_1:SPI0:BSPIM:tx_status_1\ ,
            status_0 => \emFile_1:SPI0:BSPIM:tx_status_0\ );
        Properties:
        {
            cy_force_order = 1
            cy_int_mask = "0000000"
            cy_md_select = "0001001"
        }
        Clock Polarity: Active High
        Clock Enable: True

    statusicell: Name =\emFile_1:SPI0:BSPIM:RxStsReg\
        PORT MAP (
            clock => \emFile_1:Net_19\ ,
            status_6 => \emFile_1:SPI0:BSPIM:rx_status_6\ ,
            status_5 => \emFile_1:SPI0:BSPIM:rx_status_5\ ,
            status_4 => \emFile_1:SPI0:BSPIM:rx_status_4\ );
        Properties:
        {
            cy_force_order = 1
            cy_int_mask = "0000000"
            cy_md_select = "1000000"
        }
        Clock Polarity: Active High
        Clock Enable: True
    </CYPRESSTAG>
    <CYPRESSTAG name="Sync listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Control register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Count7 listing">

    ------------------------------------------------------------
    Count7 listing
    ------------------------------------------------------------

    count7cell: Name =\emFile_1:SPI0:BSPIM:BitCounter\
        PORT MAP (
            clock => \emFile_1:Net_19\ ,
            enable => \emFile_1:SPI0:BSPIM:cnt_enable\ ,
            count_6 => \emFile_1:SPI0:BSPIM:count_6\ ,
            count_5 => \emFile_1:SPI0:BSPIM:count_5\ ,
            count_4 => \emFile_1:SPI0:BSPIM:count_4\ ,
            count_3 => \emFile_1:SPI0:BSPIM:count_3\ ,
            count_2 => \emFile_1:SPI0:BSPIM:count_2\ ,
            count_1 => \emFile_1:SPI0:BSPIM:count_1\ ,
            count_0 => \emFile_1:SPI0:BSPIM:count_0\ ,
            tc => \emFile_1:SPI0:BSPIM:cnt_tc\ );
        Properties:
        {
            cy_alt_mode = 0
            cy_init_value = "0000000"
            cy_period = "0001111"
            cy_route_en = 1
            cy_route_ld = 0
        }
        Clock Polarity: Active High
        Clock Enable: True
    </CYPRESSTAG>
    <CYPRESSTAG name="DRQ listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Interrupt listing">
    </CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Technology mapping summary" expanded>

------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital Clocks                :    2 :    6 :    8 : 25.00 %
Analog Clocks                 :    0 :    4 :    4 :  0.00 %
CapSense Buffers              :    0 :    2 :    2 :  0.00 %
Digital Filter Block          :    0 :    1 :    1 :  0.00 %
Interrupts                    :    0 :   32 :   32 :  0.00 %
IO                            :    9 :   39 :   48 : 18.75 %
Segment LCD                   :    0 :    1 :    1 :  0.00 %
CAN 2.0b                      :    0 :    1 :    1 :  0.00 %
I2C                           :    0 :    1 :    1 :  0.00 %
USB                           :    0 :    1 :    1 :  0.00 %
DMA Channels                  :    0 :   24 :   24 :  0.00 %
Timer                         :    1 :    3 :    4 : 25.00 %
UDB                           :      :      :      :        
  Macrocells                  :   20 :  172 :  192 : 10.42 %
  Unique P-terms              :   48 :  336 :  384 : 12.50 %
  Total P-terms               :   54 :      :      :        
  Datapath Cells              :    1 :   23 :   24 :  4.17 %
  Status Cells                :    3 :   21 :   24 : 12.50 %
    StatusI Registers         :    2 :      :      :        
    Routed Count7 Load/Enable :    1 :      :      :        
  Control Cells               :    1 :   23 :   24 :  4.17 %
    Count7 Cells              :    1 :      :      :        
Opamp                         :    0 :    4 :    4 :  0.00 %
Comparator                    :    0 :    4 :    4 :  0.00 %
Delta-Sigma ADC               :    0 :    1 :    1 :  0.00 %
LPF                           :    0 :    2 :    2 :  0.00 %
SAR ADC                       :    0 :    2 :    2 :  0.00 %
Analog (SC/CT) Blocks         :    0 :    4 :    4 :  0.00 %
DAC                           :      :      :      :        
  VIDAC                       :    0 :    4 :    4 :  0.00 %
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.296ms
Tech Mapping phase: Elapsed time ==> 0s.421ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
Initial Analog Placement Results:
IO_2@[IOP=(2)][IoId=(2)] : Kill_Switch(0) (fixed)
IO_1@[IOP=(2)][IoId=(1)] : PWM_Out_1(0) (fixed)
IO_4@[IOP=(1)][IoId=(4)] : \emFile_1:SPI0_CS(0)\ (fixed)
IO_7@[IOP=(1)][IoId=(7)] : \emFile_1:miso0(0)\ (fixed)
IO_6@[IOP=(1)][IoId=(6)] : \emFile_1:mosi0(0)\ (fixed)
IO_5@[IOP=(1)][IoId=(5)] : \emFile_1:sclk0(0)\ (fixed)
Analog Placement phase: Elapsed time ==> 0s.109ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
Analog Routing phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Code Generation">
============ Analog Final Answer Routes ============
Dump of CyAnalogRoutingResultsDB
Map of net to items {
}
Map of item to net {
}
Mux Info {
}
Dump of CyP35AnalogRoutingResultsDB
IsVddaHalfUsedForComp = False
IsVddaHalfUsedForSar0 = False
IsVddaHalfUsedForSar1 = False
Analog Code Generation phase: Elapsed time ==> 0s.561ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages">
I2076: Total run-time: 2.2 sec.

</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
<CYPRESSTAG name="PLD Packing Summary" expanded>

------------------------------------------------------------
PLD Packing Summary
------------------------------------------------------------
            Resource Type : Used : Free :  Max :  % Used
    ====================================================
                     PLDs :    9 :   39 :   48 :  18.75%

<CYPRESSTAG name="PLD Statistics">

        PLD Resource Type :     Average/LAB
    =======================================
                   Inputs :            8.67
                   Pterms :            5.78
               Macrocells :            2.22
</CYPRESSTAG>
<CYPRESSTAG name="Packed PLD Contents">
Packed PLD Contents not displayed at this verbose level.</CYPRESSTAG>
</CYPRESSTAG>
PLD Packing: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Partitioning">
<CYPRESSTAG name="Initial Partitioning Summary">
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.031ms
</CYPRESSTAG>
<CYPRESSTAG name="Final Placement Summary">

------------------------------------------------------------
Final Placement Summary
------------------------------------------------------------

       Resource Type :      Count : Avg Inputs : Avg Outputs
    ========================================================
                 UDB :          5 :       9.60 :       4.00
<CYPRESSTAG name="Final Placement Details">
<CYPRESSTAG name="Component Details">

------------------------------------------------------------
Component Placement Details
------------------------------------------------------------
UDB [UDB=(0,0)] is empty.
UDB [UDB=(0,1)] is empty.
UDB [UDB=(0,2)] contents:
LAB@[UDB=(0,2)][LB=0] #macrocells=3, #inputs=6, #pterms=5
{
    [McSlotId=0]:     MacroCell: Name=\emFile_1:Net_22\, Mode=(D-Register) @ [UDB=(0,2)][LB=0][MC=0]
        Total # of inputs        : 4
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        (
              \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:Net_22\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:Net_22\ (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=1]:     MacroCell: Name=Net_267, Mode=(Combinatorial) @ [UDB=(0,2)][LB=0][MC=1]
        Total # of inputs        : 1
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !Net_268
        );
        Output = Net_267 (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=2]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_from_dp_reg\, Mode=(D-Register) @ [UDB=(0,2)][LB=0][MC=2]
        Total # of inputs        : 1
        Total # of product terms : 1
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              \emFile_1:SPI0:BSPIM:mosi_from_dp\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\ (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=3]: (empty)
}

LAB@[UDB=(0,2)][LB=1] #macrocells=1, #inputs=6, #pterms=4
{
    [McSlotId=0]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_hs_reg\, Mode=(D-Register) @ [UDB=(0,2)][LB=1][MC=0]
        Total # of inputs        : 6
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp_reg\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\
            + !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
            + !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_hs_reg\ (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=1]: (empty)
    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

UDB [UDB=(0,3)] is empty.
UDB [UDB=(0,4)] is empty.
UDB [UDB=(0,5)] is empty.
UDB [UDB=(1,0)] contents:
LAB@[UDB=(1,0)][LB=0] #macrocells=4, #inputs=12, #pterms=8
{
    [McSlotId=0]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:state_0\, Mode=(T-Register) @ [UDB=(1,0)][LB=0][MC=0]
        Total # of inputs        : 10
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:tx_status_1\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * \emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
        );
        Output = \emFile_1:SPI0:BSPIM:state_0\ (fanout=15)
        Properties               : 
        {
        }

    [McSlotId=1]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_pre_reg\, Mode=(D-Register) @ [UDB=(1,0)][LB=0][MC=1]
        Total # of inputs        : 2
        Total # of product terms : 1
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 1 pterm
        !(
              !\emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ * 
              !\emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_pre_reg\ (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=2]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:state_1\, Mode=(D-Register) @ [UDB=(1,0)][LB=0][MC=2]
        Total # of inputs        : 10
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              \emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * \emFile_1:SPI0:BSPIM:count_2\ * 
              \emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:tx_status_1\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:state_1\ (fanout=15)
        Properties               : 
        {
        }

    [McSlotId=3]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:tx_status_0\, Mode=(Combinatorial) @ [UDB=(1,0)][LB=0][MC=3]
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:tx_status_0\ (fanout=1)
        Properties               : 
        {
        }
}

LAB@[UDB=(1,0)][LB=1] #macrocells=2, #inputs=11, #pterms=8
{
    [McSlotId=0]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\, Mode=(Combinatorial) @ [UDB=(1,0)][LB=1][MC=0]
        Total # of inputs        : 10
        Total # of product terms : 6
            Clock Enable: True
        Main Equation            : 6 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
            + !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_0\
            + !\emFile_1:SPI0:BSPIM:state_2\ * 
              !\emFile_1:SPI0:BSPIM:mosi_pre_reg\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * 
              !\emFile_1:SPI0:BSPIM:mosi_from_dp\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_pre_reg_split_1\ (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=1]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:ld_ident\, Mode=(T-Register) @ [UDB=(1,0)][LB=1][MC=1]
        Total # of inputs        : 9
        Total # of product terms : 2
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 2 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * \emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:ld_ident\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
        );
        Output = \emFile_1:SPI0:BSPIM:ld_ident\ (fanout=6)
        Properties               : 
        {
        }

    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

statusicell: Name =\emFile_1:SPI0:BSPIM:TxStsReg\
    PORT MAP (
        clock => \emFile_1:Net_19\ ,
        status_4 => \emFile_1:SPI0:BSPIM:tx_status_4\ ,
        status_3 => \emFile_1:SPI0:BSPIM:load_rx_data\ ,
        status_2 => \emFile_1:SPI0:BSPIM:tx_status_2\ ,
        status_1 => \emFile_1:SPI0:BSPIM:tx_status_1\ ,
        status_0 => \emFile_1:SPI0:BSPIM:tx_status_0\ );
    Properties:
    {
        cy_force_order = 1
        cy_int_mask = "0000000"
        cy_md_select = "0001001"
    }
    Clock Polarity: Active High
    Clock Enable: True

UDB [UDB=(1,1)] contents:
LAB@[UDB=(1,1)][LB=0] #macrocells=1, #inputs=11, #pterms=8
{
    [McSlotId=0]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:mosi_pre_reg_split\, Mode=(Combinatorial) @ [UDB=(1,1)][LB=0][MC=0]
        Total # of inputs        : 11
        Total # of product terms : 8
            Clock Enable: True
        Main Equation            : 8 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_4\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_3\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_2\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              \emFile_1:SPI0:BSPIM:count_1\
            + !\emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              !\emFile_1:SPI0:BSPIM:count_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_pre_reg\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              \emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_pre_reg\
            + \emFile_1:SPI0:BSPIM:state_1\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:mosi_from_dp\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
        );
        Output = \emFile_1:SPI0:BSPIM:mosi_pre_reg_split\ (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=1]: (empty)
    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

LAB@[UDB=(1,1)][LB=1] #macrocells=4, #inputs=11, #pterms=8
{
    [McSlotId=0]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:state_2\, Mode=(D-Register) @ [UDB=(1,1)][LB=1][MC=0]
        Total # of inputs        : 10
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_1\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * \emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:ld_ident\
            + \emFile_1:SPI0:BSPIM:state_1\ * \emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              \emFile_1:SPI0:BSPIM:count_2\ * \emFile_1:SPI0:BSPIM:count_1\ * 
              !\emFile_1:SPI0:BSPIM:count_0\ * 
              !\emFile_1:SPI0:BSPIM:tx_status_1\
        );
        Output = \emFile_1:SPI0:BSPIM:state_2\ (fanout=15)
        Properties               : 
        {
        }

    [McSlotId=1]:     MacroCell: Name=\emFile_1:Net_1\, Mode=(D-Register) @ [UDB=(1,1)][LB=1][MC=1]
        Total # of inputs        : 4
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        !(
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:Net_1\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:Net_1\
        );
        Output = \emFile_1:Net_1\ (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=2]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:load_rx_data\, Mode=(Combinatorial) @ [UDB=(1,1)][LB=1][MC=2]
        Total # of inputs        : 5
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              \emFile_1:SPI0:BSPIM:count_0\
        );
        Output = \emFile_1:SPI0:BSPIM:load_rx_data\ (fanout=2)
        Properties               : 
        {
        }

    [McSlotId=3]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:tx_status_4\, Mode=(Combinatorial) @ [UDB=(1,1)][LB=1][MC=3]
        Total # of inputs        : 3
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\
        );
        Output = \emFile_1:SPI0:BSPIM:tx_status_4\ (fanout=1)
        Properties               : 
        {
        }
}

datapathcell: Name =\emFile_1:SPI0:BSPIM:sR8:Dp:u0\
    PORT MAP (
        clock => \emFile_1:Net_19\ ,
        cs_addr_2 => \emFile_1:SPI0:BSPIM:state_2\ ,
        cs_addr_1 => \emFile_1:SPI0:BSPIM:state_1\ ,
        cs_addr_0 => \emFile_1:SPI0:BSPIM:state_0\ ,
        route_si => \emFile_1:Net_16\ ,
        f1_load => \emFile_1:SPI0:BSPIM:load_rx_data\ ,
        so_comb => \emFile_1:SPI0:BSPIM:mosi_from_dp\ ,
        f0_bus_stat_comb => \emFile_1:SPI0:BSPIM:tx_status_2\ ,
        f0_blk_stat_comb => \emFile_1:SPI0:BSPIM:tx_status_1\ ,
        f1_bus_stat_comb => \emFile_1:SPI0:BSPIM:rx_status_5\ ,
        f1_blk_stat_comb => \emFile_1:SPI0:BSPIM:rx_status_4\ );
    Properties:
    {
        a0_init = "00000000"
        a1_init = "00000000"
        ce0_sync = 1
        ce1_sync = 1
        cl0_sync = 1
        cl1_sync = 1
        cmsb_sync = 1
        co_msb_sync = 1
        cy_dpconfig = "0000000000000000000000001100000000000001010000000001000100010000000000011100000000010001000000000000000101000000000000010100000011111111000000001111111111111111000000000010001000001000111100000000000000000100"
        d0_init = "00000000"
        d1_init = "00000000"
        f0_blk_sync = 1
        f0_bus_sync = 1
        f1_blk_sync = 1
        f1_bus_sync = 1
        ff0_sync = 1
        ff1_sync = 1
        ov_msb_sync = 1
        so_sync = 1
        z0_sync = 1
        z1_sync = 1
    }
    Clock Polarity: Active High
    Clock Enable: True

count7cell: Name =\emFile_1:SPI0:BSPIM:BitCounter\
    PORT MAP (
        clock => \emFile_1:Net_19\ ,
        enable => \emFile_1:SPI0:BSPIM:cnt_enable\ ,
        count_6 => \emFile_1:SPI0:BSPIM:count_6\ ,
        count_5 => \emFile_1:SPI0:BSPIM:count_5\ ,
        count_4 => \emFile_1:SPI0:BSPIM:count_4\ ,
        count_3 => \emFile_1:SPI0:BSPIM:count_3\ ,
        count_2 => \emFile_1:SPI0:BSPIM:count_2\ ,
        count_1 => \emFile_1:SPI0:BSPIM:count_1\ ,
        count_0 => \emFile_1:SPI0:BSPIM:count_0\ ,
        tc => \emFile_1:SPI0:BSPIM:cnt_tc\ );
    Properties:
    {
        cy_alt_mode = 0
        cy_init_value = "0000000"
        cy_period = "0001111"
        cy_route_en = 1
        cy_route_ld = 0
    }
    Clock Polarity: Active High
    Clock Enable: True

UDB [UDB=(1,2)] contents:
LAB@[UDB=(1,2)][LB=0] #macrocells=2, #inputs=10, #pterms=7
{
    [McSlotId=0]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:load_cond\, Mode=(T-Register) @ [UDB=(1,2)][LB=0][MC=0]
        Total # of inputs        : 9
        Total # of product terms : 4
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 4 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:load_cond\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:load_cond\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:load_cond\
            + \emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:SPI0:BSPIM:count_4\ * 
              !\emFile_1:SPI0:BSPIM:count_3\ * !\emFile_1:SPI0:BSPIM:count_2\ * 
              !\emFile_1:SPI0:BSPIM:count_1\ * !\emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:load_cond\
        );
        Output = \emFile_1:SPI0:BSPIM:load_cond\ (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=1]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:cnt_enable\, Mode=(T-Register) @ [UDB=(1,2)][LB=0][MC=1]
        Total # of inputs        : 4
        Total # of product terms : 3
        List of special equations: 
            Clock  = (\emFile_1:Net_19\) => Global
            Clock Enable: True
        Main Equation            : 3 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:cnt_enable\
            + \emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:SPI0:BSPIM:state_1\ * 
              \emFile_1:SPI0:BSPIM:state_0\ * 
              \emFile_1:SPI0:BSPIM:cnt_enable\
            + \emFile_1:SPI0:BSPIM:state_2\ * \emFile_1:SPI0:BSPIM:state_1\ * 
              !\emFile_1:SPI0:BSPIM:state_0\ * 
              !\emFile_1:SPI0:BSPIM:cnt_enable\
        );
        Output = \emFile_1:SPI0:BSPIM:cnt_enable\ (fanout=3)
        Properties               : 
        {
        }

    [McSlotId=2]: (empty)
    [McSlotId=3]: (empty)
}

LAB@[UDB=(1,2)][LB=1] #macrocells=2, #inputs=11, #pterms=4
{
    [McSlotId=0]: (empty)
    [McSlotId=1]:     MacroCell: Name=\emFile_1:SPI0:BSPIM:rx_status_6\, Mode=(Combinatorial) @ [UDB=(1,2)][LB=1][MC=1]
        Total # of inputs        : 6
        Total # of product terms : 1
            Clock Enable: True
        Main Equation            : 1 pterm
        (
              !\emFile_1:SPI0:BSPIM:count_4\ * !\emFile_1:SPI0:BSPIM:count_3\ * 
              !\emFile_1:SPI0:BSPIM:count_2\ * !\emFile_1:SPI0:BSPIM:count_1\ * 
              \emFile_1:SPI0:BSPIM:count_0\ * 
              \emFile_1:SPI0:BSPIM:rx_status_4\
        );
        Output = \emFile_1:SPI0:BSPIM:rx_status_6\ (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=2]:     MacroCell: Name=\emFile_1:Net_10\, Mode=(Combinatorial) @ [UDB=(1,2)][LB=1][MC=2]
        Total # of inputs        : 5
        Total # of product terms : 3
            Clock Enable: True
        Main Equation            : 3 pterms
        (
              !\emFile_1:SPI0:BSPIM:state_2\ * !\emFile_1:Net_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
            + \emFile_1:SPI0:BSPIM:state_1\ * !\emFile_1:Net_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
            + !\emFile_1:SPI0:BSPIM:state_0\ * !\emFile_1:Net_1\ * 
              \emFile_1:SPI0:BSPIM:mosi_hs_reg\
        );
        Output = \emFile_1:Net_10\ (fanout=1)
        Properties               : 
        {
        }

    [McSlotId=3]: (empty)
}

statusicell: Name =\emFile_1:SPI0:BSPIM:RxStsReg\
    PORT MAP (
        clock => \emFile_1:Net_19\ ,
        status_6 => \emFile_1:SPI0:BSPIM:rx_status_6\ ,
        status_5 => \emFile_1:SPI0:BSPIM:rx_status_5\ ,
        status_4 => \emFile_1:SPI0:BSPIM:rx_status_4\ );
    Properties:
    {
        cy_force_order = 1
        cy_int_mask = "0000000"
        cy_md_select = "1000000"
    }
    Clock Polarity: Active High
    Clock Enable: True

UDB [UDB=(1,3)] is empty.
UDB [UDB=(1,4)] is empty.
UDB [UDB=(1,5)] is empty.
UDB [UDB=(2,0)] is empty.
UDB [UDB=(2,1)] is empty.
UDB [UDB=(2,2)] is empty.
UDB [UDB=(2,3)] is empty.
UDB [UDB=(2,4)] is empty.
UDB [UDB=(2,5)] is empty.
UDB [UDB=(3,0)] is empty.
UDB [UDB=(3,1)] is empty.
UDB [UDB=(3,2)] is empty.
UDB [UDB=(3,3)] is empty.
UDB [UDB=(3,4)] contents:
LAB@[UDB=(3,4)][LB=1] #macrocells=1, #inputs=0, #pterms=0
{
    [McSlotId=0]: (empty)
    [McSlotId=1]: (empty)
    [McSlotId=2]: (empty)
    [McSlotId=3]:     MacroCell: Name=__ONE__, Mode=(Combinatorial) @ [UDB=(3,4)][LB=1][MC=3]
        Total # of inputs        : 0
        Total # of product terms : 0
            Clock Enable: True
        Main Equation            : 0 pterms
        !(
            0
        );
        Output = __ONE__ (fanout=1)
        Properties               : 
        {
        }
}

UDB [UDB=(3,5)] is empty.
Intr container @ [IntrContainer=(0)]: empty
Drq container @ [DrqContainer=(0)]: empty
Port 0 contains the following IO cells:
Port 1 contains the following IO cells:
[IoId=4]: 
Pin : Name = \emFile_1:SPI0_CS(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \emFile_1:SPI0_CS(0)\__PA ,
        pad => \emFile_1:SPI0_CS(0)_PAD\ );
    Properties:
    {
    }

[IoId=5]: 
Pin : Name = \emFile_1:sclk0(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \emFile_1:sclk0(0)\__PA ,
        pin_input => \emFile_1:Net_22\ ,
        pad => \emFile_1:sclk0(0)_PAD\ );
    Properties:
    {
    }

[IoId=6]: 
Pin : Name = \emFile_1:mosi0(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \emFile_1:mosi0(0)\__PA ,
        pin_input => \emFile_1:Net_10\ ,
        pad => \emFile_1:mosi0(0)_PAD\ );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = \emFile_1:miso0(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: NOSYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_DIGITAL
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \emFile_1:miso0(0)\__PA ,
        fb => \emFile_1:Net_16\ ,
        pad => \emFile_1:miso0(0)_PAD\ );
    Properties:
    {
    }

Port 2 contains the following IO cells:
[IoId=1]: 
Pin : Name = PWM_Out_1(0)
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: CMOS_OUT
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => PWM_Out_1(0)__PA ,
        pin_input => Net_254 ,
        annotation => Net_260 ,
        pad => PWM_Out_1(0)_PAD );
    Properties:
    {
    }

[IoId=2]: 
Pin : Name = Kill_Switch(0)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: RES_PULL_UP
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => Kill_Switch(0)__PA ,
        fb => Net_268 ,
        annotation => Net_264 ,
        pad => Kill_Switch(0)_PAD );
    Properties:
    {
    }

Port 3 contains the following IO cells:
Port 12 contains the following IO cells:
Port 15 contains the following IO cells:
ARM group 0: empty
CAN group 0: empty
Cache group 0: empty
CapSense group 0: empty
Clock group 0: 
    Clock Block @ F(Clock,0): 
    clockblockcell: Name =ClockBlock
        PORT MAP (
            imo => ClockBlock_IMO ,
            pllout => ClockBlock_PLL_OUT ,
            ilo => ClockBlock_ILO ,
            clk_100k => ClockBlock_100k ,
            clk_1k => ClockBlock_1k ,
            clk_32k => ClockBlock_32k ,
            xtal => ClockBlock_XTAL ,
            clk_32k_xtal => ClockBlock_XTAL_32KHZ ,
            clk_sync => ClockBlock_MASTER_CLK ,
            clk_bus_glb => ClockBlock_BUS_CLK ,
            clk_bus => ClockBlock_BUS_CLK_local ,
            dclk_glb_0 => \emFile_1:Net_19\ ,
            dclk_0 => \emFile_1:Net_19_local\ ,
            dclk_glb_1 => Net_134 ,
            dclk_1 => Net_134_local );
        Properties:
        {
        }
Comparator group 0: empty
DFB group 0: empty
DSM group 0: empty
Decimator group 0: empty
EMIF group 0: empty
I2C group 0: empty
LCD group 0: empty
LVD group 0: empty
PICU group 0: empty
PM group 0: empty
SC group 0: empty
SPC group 0: empty
Timer group 0: 
    Timer Block @ F(Timer,0): 
    timercell: Name =\PWM_1:PWMHW\
        PORT MAP (
            clock => Net_134 ,
            kill => Net_267 ,
            enable => __ONE__ ,
            tc => \PWM_1:Net_63\ ,
            cmp => Net_254 ,
            irq => \PWM_1:Net_54\ );
        Properties:
        {
            cy_registers = ""
        }
USB group 0: empty
VIDAC group 0: empty
OpAmp group 0: empty
CsAbuf group 0: empty
Vref group 0: empty
LPF group 0: empty
SAR group 0: empty
ANAIF group 0: empty
PHUB group 0: empty
</CYPRESSTAG>
<CYPRESSTAG name="Port Configuration Details">

------------------------------------------------------------
Port Configuration report
------------------------------------------------------------
     |     |       | Interrupt |                  |                       | 
Port | Pin | Fixed |      Type |       Drive Mode |                  Name | Connections
-----+-----+-------+-----------+------------------+-----------------------+----------------------
   1 |   4 |     * |      NONE |         CMOS_OUT | \emFile_1:SPI0_CS(0)\ | 
     |   5 |     * |      NONE |         CMOS_OUT |   \emFile_1:sclk0(0)\ | In(\emFile_1:Net_22\)
     |   6 |     * |      NONE |         CMOS_OUT |   \emFile_1:mosi0(0)\ | In(\emFile_1:Net_10\)
     |   7 |     * |      NONE |     HI_Z_DIGITAL |   \emFile_1:miso0(0)\ | FB(\emFile_1:Net_16\)
-----+-----+-------+-----------+------------------+-----------------------+----------------------
   2 |   1 |     * |      NONE |         CMOS_OUT |          PWM_Out_1(0) | In(Net_254)
     |   2 |     * |      NONE |      RES_PULL_UP |        Kill_Switch(0) | FB(Net_268)
-------------------------------------------------------------------------------------------------
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.156ms
Digital Placement phase: Elapsed time ==> 3s.385ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
"C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc5/psoc5lp/route_arch-rrg.cydata" --vh2-path "CE195352_PSoC_5LP_FATFS_r.vh2" --pcf-path "CE195352_PSoC_5LP_FATFS.pco" --des-name "CE195352_PSoC_5LP_FATFS" --dsf-path "CE195352_PSoC_5LP_FATFS.dsf" --sdc-path "CE195352_PSoC_5LP_FATFS.sdc" --lib-path "CE195352_PSoC_5LP_FATFS_r.lib"
Routing successful.
Digital Routing phase: Elapsed time ==> 3s.900ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Generation">
Bitstream Generation phase: Elapsed time ==> 0s.421ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Verification">
Bitstream Verification phase: Elapsed time ==> 0s.140ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
Timing report is in CE195352_PSoC_5LP_FATFS_timing.html.
Static timing analysis phase: Elapsed time ==> 2s.043ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.390ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 11s.466ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 11s.466ms
API generation phase: Elapsed time ==> 6s.598ms
Dependency generation phase: Elapsed time ==> 0s.046ms
Cleanup phase: Elapsed time ==> 0s.031ms
