Static Timing Analysis

Project : 5LP_v0_3_16bits
Build Time : 03/29/18 02:28:59
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
SPI_IntClock CyMASTER_CLK 2.000 MHz 2.000 MHz 66.796 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPI:BSPIM:state_2\/q \SPI:BSPIM:TxStsReg\/status_0 66.796 MHz 14.971 485.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,1) 1 \SPI:BSPIM:state_2\ \SPI:BSPIM:state_2\/clock_0 \SPI:BSPIM:state_2\/q 1.250
Route 1 \SPI:BSPIM:state_2\ \SPI:BSPIM:state_2\/q \SPI:BSPIM:tx_status_0\/main_0 5.712
macrocell2 U(3,2) 1 \SPI:BSPIM:tx_status_0\ \SPI:BSPIM:tx_status_0\/main_0 \SPI:BSPIM:tx_status_0\/q 3.350
Route 1 \SPI:BSPIM:tx_status_0\ \SPI:BSPIM:tx_status_0\/q \SPI:BSPIM:TxStsReg\/status_0 4.159
statusicell1 U(3,2) 1 \SPI:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPI:BSPIM:state_0\/q \SPI:BSPIM:TxStsReg\/status_0 68.227 MHz 14.657 485.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(2,1) 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/clock_0 \SPI:BSPIM:state_0\/q 1.250
Route 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/q \SPI:BSPIM:tx_status_0\/main_2 5.398
macrocell2 U(3,2) 1 \SPI:BSPIM:tx_status_0\ \SPI:BSPIM:tx_status_0\/main_2 \SPI:BSPIM:tx_status_0\/q 3.350
Route 1 \SPI:BSPIM:tx_status_0\ \SPI:BSPIM:tx_status_0\/q \SPI:BSPIM:TxStsReg\/status_0 4.159
statusicell1 U(3,2) 1 \SPI:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:sR16:Dp:u0\/f1_load 68.348 MHz 14.631 485.369
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:load_rx_data\/main_2 3.697
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_2 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u0\/f1_load 2.794
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:sR16:Dp:u1\/f1_load 68.446 MHz 14.610 485.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:load_rx_data\/main_2 3.697
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_2 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u1\/f1_load 2.773
datapathcell2 U(2,1) 1 \SPI:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:sR16:Dp:u0\/f1_load 70.962 MHz 14.092 485.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:load_rx_data\/main_0 3.158
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_0 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u0\/f1_load 2.794
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:sR16:Dp:u1\/f1_load 71.068 MHz 14.071 485.929
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:load_rx_data\/main_0 3.158
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_0 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u1\/f1_load 2.773
datapathcell2 U(2,1) 1 \SPI:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:sR16:Dp:u0\/f1_load 71.948 MHz 13.899 486.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_rx_data\/main_1 2.965
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_1 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u0\/f1_load 2.794
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:sR16:Dp:u1\/f1_load 72.056 MHz 13.878 486.122
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_rx_data\/main_1 2.965
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_1 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u1\/f1_load 2.773
datapathcell2 U(2,1) 1 \SPI:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:sR16:Dp:u0\/f1_load 73.725 MHz 13.564 486.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPI:BSPIM:count_0\ \SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:load_rx_data\/main_4 2.630
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_4 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u0\/f1_load 2.794
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:sR16:Dp:u0\/f1_load 73.812 MHz 13.548 486.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPI:BSPIM:count_1\ \SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:load_rx_data\/main_3 2.614
macrocell1 U(2,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_3 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR16:Dp:u0\/f1_load 2.794
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPI:BSPIM:sR16:Dp:u0\/sol_msb \SPI:BSPIM:sR16:Dp:u1\/sir 0.170
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR16:Dp:u0\ \SPI:BSPIM:sR16:Dp:u0\/clock \SPI:BSPIM:sR16:Dp:u0\/sol_msb 0.170
Route 1 \SPI:BSPIM:sR16:Dp:u0.sol_msb__sig\ \SPI:BSPIM:sR16:Dp:u0\/sol_msb \SPI:BSPIM:sR16:Dp:u1\/sir 0.000
datapathcell2 U(2,1) 1 \SPI:BSPIM:sR16:Dp:u1\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:load_cond\/main_6 3.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPI:BSPIM:count_1\ \SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:load_cond\/main_6 2.605
macrocell11 U(2,1) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:ld_ident\/main_6 3.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPI:BSPIM:count_1\ \SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:ld_ident\/main_6 2.605
macrocell12 U(2,1) 1 \SPI:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:state_2\/main_6 3.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPI:BSPIM:count_1\ \SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:state_2\/main_6 2.614
macrocell7 U(2,1) 1 \SPI:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:load_cond\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPI:BSPIM:count_0\ \SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:load_cond\/main_7 2.616
macrocell11 U(2,1) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:ld_ident\/main_7 3.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPI:BSPIM:count_0\ \SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:ld_ident\/main_7 2.616
macrocell12 U(2,1) 1 \SPI:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:state_2\/main_7 3.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPI:BSPIM:count_0\ \SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:state_2\/main_7 2.630
macrocell7 U(2,1) 1 \SPI:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
Net_24/q Net_24/main_3 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,2) 1 Net_24 Net_24/clock_0 Net_24/q 1.250
macrocell10 U(3,2) 1 Net_24 Net_24/q Net_24/main_3 2.297
macrocell10 U(3,2) 1 Net_24 HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:load_cond\/q \SPI:BSPIM:load_cond\/main_8 3.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \SPI:BSPIM:load_cond\ \SPI:BSPIM:load_cond\/clock_0 \SPI:BSPIM:load_cond\/q 1.250
macrocell11 U(2,1) 1 \SPI:BSPIM:load_cond\ \SPI:BSPIM:load_cond\/q \SPI:BSPIM:load_cond\/main_8 2.316
macrocell11 U(2,1) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_cond\/main_4 3.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_cond\/main_4 2.954
macrocell11 U(2,1) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPI_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \SPI:BSPIM:sR16:Dp:u0\/route_si 17.378
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell1 P12[0] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 6.830
Route 1 Net_19 MISO(0)/fb \SPI:BSPIM:sR16:Dp:u0\/route_si 7.048
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR16:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPI_IntClock
Source Destination Delay (ns)
Net_23/q MOSI(0)_PAD 24.091
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,2) 1 Net_23 Net_23/clock_0 Net_23/q 1.250
Route 1 Net_23 Net_23/q MOSI(0)/pin_input 6.908
iocell2 P12[1] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 15.933
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_25/q SCLK(0)_PAD 23.055
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,2) 1 Net_25 Net_25/clock_0 Net_25/q 1.250
Route 1 Net_25 Net_25/q SCLK(0)/pin_input 6.139
iocell3 P12[2] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 15.666
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000