Static Timing Analysis

Project : GPS_Shield
Build Time : 02/02/18 16:46:58
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
CyHFCLK Clock -0.968
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 45.869 MHz Frequency
UART_DBG_SCBCLK CyHFCLK 115.108 kHz 115.108 kHz N/A
Clock CyHFCLK 76.800 kHz 76.800 kHz 42.056 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
UART_DBG_SCBCLK(FFB) UART_DBG_SCBCLK(FFB) 115.108 kHz 115.108 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 13020.8ns(76.8 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_G:BUART:tx_state_1\/q \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.056 MHz 23.778 12997.055
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,1) 1 \UART_G:BUART:tx_state_1\ \UART_G:BUART:tx_state_1\/clock_0 \UART_G:BUART:tx_state_1\/q 1.250
Route 1 \UART_G:BUART:tx_state_1\ \UART_G:BUART:tx_state_1\/q \UART_G:BUART:counter_load_not\/main_0 5.356
macrocell2 U(0,1) 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/main_0 \UART_G:BUART:counter_load_not\/q 3.350
Route 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/q \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_G:BUART:tx_state_2\/q \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.931 MHz 23.293 12997.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,1) 1 \UART_G:BUART:tx_state_2\ \UART_G:BUART:tx_state_2\/clock_0 \UART_G:BUART:tx_state_2\/q 1.250
Route 1 \UART_G:BUART:tx_state_2\ \UART_G:BUART:tx_state_2\/q \UART_G:BUART:counter_load_not\/main_3 4.871
macrocell2 U(0,1) 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/main_3 \UART_G:BUART:counter_load_not\/q 3.350
Route 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/q \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_G:BUART:tx_state_0\/q \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.175 MHz 22.136 12998.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 \UART_G:BUART:tx_state_0\ \UART_G:BUART:tx_state_0\/clock_0 \UART_G:BUART:tx_state_0\/q 1.250
Route 1 \UART_G:BUART:tx_state_0\ \UART_G:BUART:tx_state_0\/q \UART_G:BUART:counter_load_not\/main_1 3.714
macrocell2 U(0,1) 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/main_1 \UART_G:BUART:counter_load_not\/q 3.350
Route 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/q \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.425 MHz 21.540 12999.293
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_G:BUART:tx_bitclk_enable_pre\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_G:BUART:counter_load_not\/main_2 3.368
macrocell2 U(0,1) 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/main_2 \UART_G:BUART:counter_load_not\/q 3.350
Route 1 \UART_G:BUART:counter_load_not\ \UART_G:BUART:counter_load_not\/q \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_G:BUART:tx_ctrl_mark_last\/q \UART_G:BUART:sRX:RxBitCounter\/load 57.071 MHz 17.522 13003.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,0) 1 \UART_G:BUART:tx_ctrl_mark_last\ \UART_G:BUART:tx_ctrl_mark_last\/clock_0 \UART_G:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_G:BUART:tx_ctrl_mark_last\ \UART_G:BUART:tx_ctrl_mark_last\/q \UART_G:BUART:rx_counter_load\/main_0 6.439
macrocell5 U(1,0) 1 \UART_G:BUART:rx_counter_load\ \UART_G:BUART:rx_counter_load\/main_0 \UART_G:BUART:rx_counter_load\/q 3.350
Route 1 \UART_G:BUART:rx_counter_load\ \UART_G:BUART:rx_counter_load\/q \UART_G:BUART:sRX:RxBitCounter\/load 2.263
count7cell U(1,0) 1 \UART_G:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_G:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_G:BUART:sTX:TxSts\/status_0 58.896 MHz 16.979 13003.854
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \UART_G:BUART:sTX:TxShifter:u0\ \UART_G:BUART:sTX:TxShifter:u0\/clock \UART_G:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_G:BUART:tx_fifo_empty\ \UART_G:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_G:BUART:tx_status_0\/main_3 4.450
macrocell3 U(1,1) 1 \UART_G:BUART:tx_status_0\ \UART_G:BUART:tx_status_0\/main_3 \UART_G:BUART:tx_status_0\/q 3.350
Route 1 \UART_G:BUART:tx_status_0\ \UART_G:BUART:tx_status_0\/q \UART_G:BUART:sTX:TxSts\/status_0 2.329
statusicell1 U(1,1) 1 \UART_G:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_G:BUART:pollcount_0\/q \UART_G:BUART:sRX:RxShifter:u0\/route_si 61.263 MHz 16.323 13004.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,1) 1 \UART_G:BUART:pollcount_0\ \UART_G:BUART:pollcount_0\/clock_0 \UART_G:BUART:pollcount_0\/q 1.250
Route 1 \UART_G:BUART:pollcount_0\ \UART_G:BUART:pollcount_0\/q \UART_G:BUART:rx_postpoll\/main_2 3.648
macrocell6 U(1,1) 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/main_2 \UART_G:BUART:rx_postpoll\/q 3.350
Route 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/q \UART_G:BUART:sRX:RxShifter:u0\/route_si 2.865
datapathcell3 U(1,0) 1 \UART_G:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_G:BUART:pollcount_1\/q \UART_G:BUART:sRX:RxShifter:u0\/route_si 61.478 MHz 16.266 13004.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,1) 1 \UART_G:BUART:pollcount_1\ \UART_G:BUART:pollcount_1\/clock_0 \UART_G:BUART:pollcount_1\/q 1.250
Route 1 \UART_G:BUART:pollcount_1\ \UART_G:BUART:pollcount_1\/q \UART_G:BUART:rx_postpoll\/main_0 3.591
macrocell6 U(1,1) 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/main_0 \UART_G:BUART:rx_postpoll\/q 3.350
Route 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/q \UART_G:BUART:sRX:RxShifter:u0\/route_si 2.865
datapathcell3 U(1,0) 1 \UART_G:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_G:BUART:tx_ctrl_mark_last\/q \UART_G:BUART:sRX:RxShifter:u0\/cs_addr_2 64.554 MHz 15.491 13005.342
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,0) 1 \UART_G:BUART:tx_ctrl_mark_last\ \UART_G:BUART:tx_ctrl_mark_last\/clock_0 \UART_G:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_G:BUART:tx_ctrl_mark_last\ \UART_G:BUART:tx_ctrl_mark_last\/q \UART_G:BUART:sRX:RxShifter:u0\/cs_addr_2 7.941
datapathcell3 U(1,0) 1 \UART_G:BUART:sRX:RxShifter:u0\ SETUP 6.300
Clock Skew 0.000
\UART_G:BUART:tx_state_2\/q \UART_G:BUART:sTX:TxSts\/status_0 67.632 MHz 14.786 13006.047
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,1) 1 \UART_G:BUART:tx_state_2\ \UART_G:BUART:tx_state_2\/clock_0 \UART_G:BUART:tx_state_2\/q 1.250
Route 1 \UART_G:BUART:tx_state_2\ \UART_G:BUART:tx_state_2\/q \UART_G:BUART:tx_status_0\/main_4 6.287
macrocell3 U(1,1) 1 \UART_G:BUART:tx_status_0\ \UART_G:BUART:tx_status_0\/main_4 \UART_G:BUART:tx_status_0\/q 3.350
Route 1 \UART_G:BUART:tx_status_0\ \UART_G:BUART:tx_status_0\/q \UART_G:BUART:sTX:TxSts\/status_0 2.329
statusicell1 U(1,1) 1 \UART_G:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_G:BUART:sRX:RxShifter:u0\/route_si 45.869 MHz 21.801 -0.968 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_postpoll\/main_1 6.329
macrocell6 U(1,1) 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/main_1 \UART_G:BUART:rx_postpoll\/q 3.350
Route 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/q \UART_G:BUART:sRX:RxShifter:u0\/route_si 2.865
datapathcell3 U(1,0) 1 \UART_G:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:pollcount_0\/main_2 72.015 MHz 13.886 6.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:pollcount_0\/main_2 6.329
macrocell22 U(1,1) 1 \UART_G:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:pollcount_1\/main_3 72.897 MHz 13.718 7.115
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:pollcount_1\/main_3 6.161
macrocell21 U(1,1) 1 \UART_G:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:rx_last\/main_0 76.669 MHz 13.043 7.790
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_last\/main_0 5.486
macrocell24 U(0,0) 1 \UART_G:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:rx_state_2\/main_8 76.722 MHz 13.034 7.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_state_2\/main_8 5.477
macrocell18 U(1,0) 1 \UART_G:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:rx_state_0\/main_9 77.670 MHz 12.875 7.958
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_state_0\/main_9 5.318
macrocell15 U(1,0) 1 \UART_G:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:rx_status_3\/main_6 77.670 MHz 12.875 7.958
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_status_3\/main_6 5.318
macrocell23 U(1,0) 1 \UART_G:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART_G:BUART:rx_status_3\/q \UART_G:BUART:sRX:RxSts\/status_3 1.504
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,0) 1 \UART_G:BUART:rx_status_3\ \UART_G:BUART:rx_status_3\/clock_0 \UART_G:BUART:rx_status_3\/q 1.250
Route 1 \UART_G:BUART:rx_status_3\ \UART_G:BUART:rx_status_3\/q \UART_G:BUART:sRX:RxSts\/status_3 2.254
statusicell2 U(0,0) 1 \UART_G:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_G:BUART:rx_last\/q \UART_G:BUART:rx_state_2\/main_9 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \UART_G:BUART:rx_last\ \UART_G:BUART:rx_last\/clock_0 \UART_G:BUART:rx_last\/q 1.250
Route 1 \UART_G:BUART:rx_last\ \UART_G:BUART:rx_last\/q \UART_G:BUART:rx_state_2\/main_9 2.232
macrocell18 U(1,0) 1 \UART_G:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:txn\/q \UART_G:BUART:txn\/main_0 3.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 \UART_G:BUART:txn\ \UART_G:BUART:txn\/clock_0 \UART_G:BUART:txn\/q 1.250
macrocell9 U(0,1) 1 \UART_G:BUART:txn\ \UART_G:BUART:txn\/q \UART_G:BUART:txn\/main_0 2.321
macrocell9 U(0,1) 1 \UART_G:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_G:BUART:tx_state_2\/main_4 3.597
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_G:BUART:tx_counter_dp\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_G:BUART:tx_state_2\/main_4 2.597
macrocell12 U(0,1) 1 \UART_G:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_G:BUART:txn\/main_5 3.605
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_G:BUART:tx_counter_dp\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_G:BUART:txn\/main_5 2.605
macrocell9 U(0,1) 1 \UART_G:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_G:BUART:tx_state_1\/main_4 3.605
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_G:BUART:tx_counter_dp\ \UART_G:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_G:BUART:tx_state_1\/main_4 2.605
macrocell10 U(0,1) 1 \UART_G:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_state_0\/main_3 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/clock_0 \UART_G:BUART:rx_state_3\/q 1.250
Route 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_state_0\/main_3 2.526
macrocell15 U(1,0) 1 \UART_G:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_load_fifo\/main_3 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/clock_0 \UART_G:BUART:rx_state_3\/q 1.250
Route 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_load_fifo\/main_3 2.526
macrocell16 U(1,0) 1 \UART_G:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_state_3\/main_3 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/clock_0 \UART_G:BUART:rx_state_3\/q 1.250
macrocell17 U(1,0) 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_state_3\/main_3 2.526
macrocell17 U(1,0) 1 \UART_G:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_status_3\/main_3 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/clock_0 \UART_G:BUART:rx_state_3\/q 1.250
Route 1 \UART_G:BUART:rx_state_3\ \UART_G:BUART:rx_state_3\/q \UART_G:BUART:rx_status_3\/main_3 2.526
macrocell23 U(1,0) 1 \UART_G:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_G:BUART:rx_state_0\/main_9 8.058
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_state_0\/main_9 5.318
macrocell15 U(1,0) 1 \UART_G:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:rx_status_3\/main_6 8.058
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_status_3\/main_6 5.318
macrocell23 U(1,0) 1 \UART_G:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:rx_state_2\/main_8 8.217
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_state_2\/main_8 5.477
macrocell18 U(1,0) 1 \UART_G:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:rx_last\/main_0 8.226
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_last\/main_0 5.486
macrocell24 U(0,0) 1 \UART_G:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:pollcount_1\/main_3 8.901
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:pollcount_1\/main_3 6.161
macrocell21 U(1,1) 1 \UART_G:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:pollcount_0\/main_2 9.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:pollcount_0\/main_2 6.329
macrocell22 U(1,1) 1 \UART_G:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_G:BUART:sRX:RxShifter:u0\/route_si 15.284
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P3[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_99 Rx_1(0)/fb \UART_G:BUART:rx_postpoll\/main_1 6.329
macrocell6 U(1,1) 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/main_1 \UART_G:BUART:rx_postpoll\/q 3.350
Route 1 \UART_G:BUART:rx_postpoll\ \UART_G:BUART:rx_postpoll\/q \UART_G:BUART:sRX:RxShifter:u0\/route_si 2.865
datapathcell3 U(1,0) 1 \UART_G:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock
Source Destination Delay (ns)
\UART_G:BUART:txn\/q Tx_1(0)_PAD 28.315
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 \UART_G:BUART:txn\ \UART_G:BUART:txn\/clock_0 \UART_G:BUART:txn\/q 1.250
Route 1 \UART_G:BUART:txn\ \UART_G:BUART:txn\/q Net_190/main_0 3.200
macrocell1 U(0,0) 1 Net_190 Net_190/main_0 Net_190/q 3.350
Route 1 Net_190 Net_190/q Tx_1(0)/pin_input 5.435
iocell10 P3[0] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.080
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyHFCLK
Source Destination Delay (ns)
\LCD:Cntl_Port:Sync:ctrl_reg\/control_5 P_3_4(0)_PAD 25.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_250 \LCD:Cntl_Port:Sync:ctrl_reg\/control_5 P_3_4(0)/pin_input 5.773
iocell1 P3[4] 1 P_3_4(0) P_3_4(0)/pin_input P_3_4(0)/pad_out 16.900
Route 1 P_3_4(0)_PAD P_3_4(0)/pad_out P_3_4(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_1 P_0_4(0)_PAD 24.774
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_253 \LCD:Cntl_Port:Sync:ctrl_reg\/control_1 P_0_4(0)/pin_input 5.604
iocell4 P0[4] 1 P_0_4(0) P_0_4(0)/pin_input P_0_4(0)/pad_out 16.590
Route 1 P_0_4(0)_PAD P_0_4(0)/pad_out P_0_4(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_0 P_0_0(0)_PAD 23.986
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_252 \LCD:Cntl_Port:Sync:ctrl_reg\/control_0 P_0_0(0)/pin_input 5.876
iocell3 P0[0] 1 P_0_0(0) P_0_0(0)/pin_input P_0_0(0)/pad_out 15.530
Route 1 P_0_0(0)_PAD P_0_0(0)/pad_out P_0_0(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_4 P_3_7(0)_PAD 23.720
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_251 \LCD:Cntl_Port:Sync:ctrl_reg\/control_4 P_3_7(0)/pin_input 5.760
iocell2 P3[7] 1 P_3_7(0) P_3_7(0)/pin_input P_3_7(0)/pad_out 15.380
Route 1 P_3_7(0)_PAD P_3_7(0)/pad_out P_3_7(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_2 P_0_5(0)_PAD 22.620
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_254 \LCD:Cntl_Port:Sync:ctrl_reg\/control_2 P_0_5(0)/pin_input 5.430
iocell5 P0[5] 1 P_0_5(0) P_0_5(0)/pin_input P_0_5(0)/pad_out 14.610
Route 1 P_0_5(0)_PAD P_0_5(0)/pad_out P_0_5(0)_PAD 0.000
Clock Clock path delay 0.000
\LCD:Cntl_Port:Sync:ctrl_reg\/control_3 P_3_5(0)_PAD 22.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \LCD:Cntl_Port:Sync:ctrl_reg\ \LCD:Cntl_Port:Sync:ctrl_reg\/busclk \LCD:Cntl_Port:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_255 \LCD:Cntl_Port:Sync:ctrl_reg\/control_3 P_3_5(0)/pin_input 5.512
iocell6 P3[6] 1 P_3_5(0) P_3_5(0)/pin_input P_3_5(0)/pad_out 14.220
Route 1 P_3_5(0)_PAD P_3_5(0)/pad_out P_3_5(0)_PAD 0.000
Clock Clock path delay 0.000