Static Timing Analysis

Project : Canary_UltraSonic_Test
Build Time : 02/07/18 11:32:26
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_3(routed) Clock_3(routed) 1.000 MHz 1.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 41.358 MHz
Clock_1 CyMASTER_CLK 6.000 MHz 6.000 MHz 62.578 MHz
Clock_3 CyMASTER_CLK 1.000 MHz 1.000 MHz N/A
Clock_2 CyMASTER_CLK 800.000 kHz 800.000 kHz 45.893 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 166.667ns(6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 62.578 MHz 15.980 150.687
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/clock \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.120
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 67.705 MHz 14.770 151.897
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/clock \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.120
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 72.202 MHz 13.850 152.817
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 1.210
Route 1 \Timer_Send:TimerUDB:control_7\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.280
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:rstSts:stsreg\/status_0 78.585 MHz 12.725 153.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/clock \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:status_tc\/main_1 3.131
macrocell26 U(3,0) 1 \Timer_Send:TimerUDB:status_tc\ \Timer_Send:TimerUDB:status_tc\/main_1 \Timer_Send:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_Send:TimerUDB:status_tc\ \Timer_Send:TimerUDB:status_tc\/q \Timer_Send:TimerUDB:rstSts:stsreg\/status_0 2.244
statusicell8 U(3,0) 1 \Timer_Send:TimerUDB:rstSts:stsreg\ SETUP 0.500
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 78.864 MHz 12.680 153.987
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/clock \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.120
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ SETUP 6.060
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 78.883 MHz 12.677 153.990
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/clock \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.117
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:rstSts:stsreg\/status_0 86.843 MHz 11.515 155.152
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/clock \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:status_tc\/main_1 3.131
macrocell26 U(3,0) 1 \Timer_Send:TimerUDB:status_tc\ \Timer_Send:TimerUDB:status_tc\/main_1 \Timer_Send:TimerUDB:status_tc\/q 3.350
Route 1 \Timer_Send:TimerUDB:status_tc\ \Timer_Send:TimerUDB:status_tc\/q \Timer_Send:TimerUDB:rstSts:stsreg\/status_0 2.244
statusicell8 U(3,0) 1 \Timer_Send:TimerUDB:rstSts:stsreg\ SETUP 0.500
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 87.184 MHz 11.470 155.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/clock \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.120
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ SETUP 6.060
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 87.207 MHz 11.467 155.200
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/clock \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.290
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.117
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
\Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_1 94.751 MHz 10.554 156.113
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 1.210
Route 1 \Timer_Send:TimerUDB:control_7\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.284
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
Path Delay Requirement : 1250ns(800 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.893 MHz 21.790 1228.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(1,2) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 8.775
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.225
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 50.898 MHz 19.647 1230.353
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,2) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 6.632
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.225
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/so_comb \UART:BUART:txn\/main_4 54.309 MHz 18.413 1231.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/so_comb 4.370
Route 1 \UART:BUART:tx_shift_out\ \UART:BUART:sTX:TxShifter:u0\/so_comb \UART:BUART:txn_split\/main_5 3.565
macrocell47 U(0,2) 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/main_5 \UART:BUART:txn_split\/q 3.350
Route 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/q \UART:BUART:txn\/main_4 3.618
macrocell28 U(0,0) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:tx_bitclk\/q \UART:BUART:txn\/main_4 56.481 MHz 17.705 1232.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(1,0) 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/clock_0 \UART:BUART:tx_bitclk\/q 1.250
Route 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/q \UART:BUART:txn_split\/main_8 5.977
macrocell47 U(0,2) 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/main_8 \UART:BUART:txn_split\/q 3.350
Route 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/q \UART:BUART:txn\/main_4 3.618
macrocell28 U(0,0) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:txn\/main_4 57.971 MHz 17.250 1232.750
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:txn_split\/main_4 5.522
macrocell47 U(0,2) 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/main_4 \UART:BUART:txn_split\/q 3.350
Route 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/q \UART:BUART:txn\/main_4 3.618
macrocell28 U(0,0) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:txn\/main_4 58.641 MHz 17.053 1232.947
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 1.210
Route 1 \UART:BUART:control_3\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:txn_split\/main_1 5.365
macrocell47 U(0,2) 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/main_1 \UART:BUART:txn_split\/q 3.350
Route 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/q \UART:BUART:txn\/main_4 3.618
macrocell28 U(0,0) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.317 MHz 16.579 1233.421
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 3.564
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.225
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:txn\/main_4 61.155 MHz 16.352 1233.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 1.210
Route 1 \UART:BUART:control_4\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:txn_split\/main_0 4.664
macrocell47 U(0,2) 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/main_0 \UART:BUART:txn_split\/q 3.350
Route 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/q \UART:BUART:txn\/main_4 3.618
macrocell28 U(0,0) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_4 62.027 MHz 16.122 1233.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn_split\/main_7 5.454
macrocell47 U(0,2) 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/main_7 \UART:BUART:txn_split\/q 3.350
Route 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/q \UART:BUART:txn\/main_4 3.618
macrocell28 U(0,0) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_4 62.181 MHz 16.082 1233.918
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn_split\/main_2 4.354
macrocell47 U(0,2) 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/main_2 \UART:BUART:txn_split\/q 3.350
Route 1 \UART:BUART:txn_split\ \UART:BUART:txn_split\/q \UART:BUART:txn\/main_4 3.618
macrocell28 U(0,0) 1 \UART:BUART:txn\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Sync:genblk1[0]:INST\/out \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 41.358 MHz 24.179 17.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync:genblk1[0]:INST\ \Sync:genblk1[0]:INST\/clock \Sync:genblk1[0]:INST\/out 1.020
Route 1 Net_568 \Sync:genblk1[0]:INST\/out \Counter_Forward:CounterUDB:count_enable\/main_0 3.760
macrocell25 U(2,3) 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/main_0 \Counter_Forward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/q \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 6.689
datapathcell13 U(0,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell14 U(1,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\Counter_Right:CounterUDB:count_stored_i\/q \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 42.488 MHz 23.536 18.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(2,2) 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/clock_0 \Counter_Right:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/q \Counter_Forward:CounterUDB:count_enable\/main_2 2.887
macrocell25 U(2,3) 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/main_2 \Counter_Forward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/q \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 6.689
datapathcell13 U(0,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell14 U(1,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\Sync:genblk1[0]:INST\/out \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 45.255 MHz 22.097 19.570
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync:genblk1[0]:INST\ \Sync:genblk1[0]:INST\/clock \Sync:genblk1[0]:INST\/out 1.020
Route 1 Net_568 \Sync:genblk1[0]:INST\/out \Counter_Left:CounterUDB:count_enable\/main_0 6.069
macrocell17 U(2,5) 1 \Counter_Left:CounterUDB:count_enable\ \Counter_Left:CounterUDB:count_enable\/main_0 \Counter_Left:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Left:CounterUDB:count_enable\ \Counter_Left:CounterUDB:count_enable\/q \Counter_Left:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.298
datapathcell9 U(2,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u0\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Left:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell10 U(3,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\Sync:genblk1[0]:INST\/out \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 45.407 MHz 22.023 19.644
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync:genblk1[0]:INST\ \Sync:genblk1[0]:INST\/clock \Sync:genblk1[0]:INST\/out 1.020
Route 1 Net_568 \Sync:genblk1[0]:INST\/out \Counter_Backward:CounterUDB:count_enable\/main_0 3.760
macrocell21 U(2,3) 1 \Counter_Backward:CounterUDB:count_enable\ \Counter_Backward:CounterUDB:count_enable\/main_0 \Counter_Backward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Backward:CounterUDB:count_enable\ \Counter_Backward:CounterUDB:count_enable\/q \Counter_Backward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 4.533
datapathcell11 U(3,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell12 U(2,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\Counter_Right:CounterUDB:count_stored_i\/q \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 46.773 MHz 21.380 20.287
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(2,2) 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/clock_0 \Counter_Right:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/q \Counter_Backward:CounterUDB:count_enable\/main_2 2.887
macrocell21 U(2,3) 1 \Counter_Backward:CounterUDB:count_enable\ \Counter_Backward:CounterUDB:count_enable\/main_2 \Counter_Backward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Backward:CounterUDB:count_enable\ \Counter_Backward:CounterUDB:count_enable\/q \Counter_Backward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 4.533
datapathcell11 U(3,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell12 U(2,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\Sync:genblk1[0]:INST\/out \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 46.900 MHz 21.322 20.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync:genblk1[0]:INST\ \Sync:genblk1[0]:INST\/clock \Sync:genblk1[0]:INST\/out 1.020
Route 1 Net_568 \Sync:genblk1[0]:INST\/out \Counter_Right:CounterUDB:count_enable\/main_0 4.517
macrocell9 U(3,4) 1 \Counter_Right:CounterUDB:count_enable\ \Counter_Right:CounterUDB:count_enable\/main_0 \Counter_Right:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Right:CounterUDB:count_enable\ \Counter_Right:CounterUDB:count_enable\/q \Counter_Right:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.075
datapathcell5 U(2,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u0\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Right:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\Sync:genblk1[0]:INST\/out \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 47.599 MHz 21.009 20.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync:genblk1[0]:INST\ \Sync:genblk1[0]:INST\/clock \Sync:genblk1[0]:INST\/out 1.020
Route 1 Net_568 \Sync:genblk1[0]:INST\/out \Counter_Forward:CounterUDB:count_enable\/main_0 3.760
macrocell25 U(2,3) 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/main_0 \Counter_Forward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/q \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 6.689
datapathcell13 U(0,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\ SETUP 6.190
Clock Skew 0.000
\Sync:genblk1[0]:INST\/out \Counter_Forward:CounterUDB:sC16:counterdp:u1\/cs_addr_1 47.685 MHz 20.971 20.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync:genblk1[0]:INST\ \Sync:genblk1[0]:INST\/clock \Sync:genblk1[0]:INST\/out 1.020
Route 1 Net_568 \Sync:genblk1[0]:INST\/out \Counter_Forward:CounterUDB:count_enable\/main_0 3.760
macrocell25 U(2,3) 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/main_0 \Counter_Forward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/q \Counter_Forward:CounterUDB:sC16:counterdp:u1\/cs_addr_1 6.651
datapathcell14 U(1,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u1\ SETUP 6.190
Clock Skew 0.000
\Counter_Right:CounterUDB:count_stored_i\/q \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 47.687 MHz 20.970 20.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(2,2) 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/clock_0 \Counter_Right:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/q \Counter_Left:CounterUDB:count_enable\/main_2 4.712
macrocell17 U(2,5) 1 \Counter_Left:CounterUDB:count_enable\ \Counter_Left:CounterUDB:count_enable\/main_2 \Counter_Left:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Left:CounterUDB:count_enable\ \Counter_Left:CounterUDB:count_enable\/q \Counter_Left:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.298
datapathcell9 U(2,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u0\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Left:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell10 U(3,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
\Counter_Right:CounterUDB:count_stored_i\/q \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 47.946 MHz 20.857 20.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(2,2) 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/clock_0 \Counter_Right:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_Right:CounterUDB:count_stored_i\ \Counter_Right:CounterUDB:count_stored_i\/q \Counter_Right:CounterUDB:count_enable\/main_2 3.822
macrocell9 U(3,4) 1 \Counter_Right:CounterUDB:count_enable\ \Counter_Right:CounterUDB:count_enable\/main_2 \Counter_Right:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Right:CounterUDB:count_enable\ \Counter_Right:CounterUDB:count_enable\/q \Counter_Right:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.075
datapathcell5 U(2,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u0\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Right:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/clock \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb 2.140
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_Send:TimerUDB:control_7\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.280
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.644
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_Send:TimerUDB:control_7\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_1 3.284
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_592/main_0 3.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_Send:TimerUDB:control_7\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_592/main_0 3.300
macrocell57 U(3,0) 1 Net_592 HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 4.927
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/clock \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 1.810
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.117
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 4.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/clock \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 1.810
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.120
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb Net_592/main_1 4.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/clock \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 1.810
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb Net_592/main_1 3.140
macrocell57 U(3,0) 1 Net_592 HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 5.430
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,0) 1 \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_Send:TimerUDB:control_7\ \Timer_Send:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_1 3.280
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb 1.790
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_Send:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 5.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/clock \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 0.280
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.350
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u1\/cs_addr_0 3.117
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 5.750
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/clock \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 0.280
Route 1 \Timer_Send:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_Send:TimerUDB:sT16:timerdp:u0\/z0 \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell16 U(3,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u1\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0i \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb 2.350
Route 1 \Timer_Send:TimerUDB:per_zero\ \Timer_Send:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_Send:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.120
datapathcell15 U(2,0) 1 \Timer_Send:TimerUDB:sT16:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_2 \UART:BUART:tx_ctrl_mark_last\/main_2 2.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_2 0.360
Route 1 \UART:BUART:control_2\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_2 \UART:BUART:tx_ctrl_mark_last\/main_2 2.243
macrocell33 U(0,0) 1 \UART:BUART:tx_ctrl_mark_last\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_2 \UART:BUART:tx_mark\/main_2 2.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_2 0.360
Route 1 \UART:BUART:control_2\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_2 \UART:BUART:tx_mark\/main_2 2.243
macrocell34 U(0,0) 1 \UART:BUART:tx_mark\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_mark\/main_6 2.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_mark\/main_6 2.690
macrocell34 U(0,0) 1 \UART:BUART:tx_mark\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_0\/main_7 2.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_0\/main_7 2.700
macrocell30 U(0,0) 1 \UART:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:tx_ctrl_mark_last\/main_0 3.073
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 0.360
Route 1 \UART:BUART:control_4\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:tx_ctrl_mark_last\/main_0 2.713
macrocell33 U(0,0) 1 \UART:BUART:tx_ctrl_mark_last\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:tx_mark\/main_0 3.073
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 0.360
Route 1 \UART:BUART:control_4\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:tx_mark\/main_0 2.713
macrocell34 U(0,0) 1 \UART:BUART:tx_mark\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:tx_state_0\/main_0 3.087
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 0.360
Route 1 \UART:BUART:control_4\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_4 \UART:BUART:tx_state_0\/main_0 2.727
macrocell30 U(0,0) 1 \UART:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:tx_ctrl_mark_last\/main_1 3.193
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 0.360
Route 1 \UART:BUART:control_3\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:tx_ctrl_mark_last\/main_1 2.833
macrocell33 U(0,0) 1 \UART:BUART:tx_ctrl_mark_last\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:tx_mark\/main_1 3.193
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 0.360
Route 1 \UART:BUART:control_3\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:tx_mark\/main_1 2.833
macrocell34 U(0,0) 1 \UART:BUART:tx_mark\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:tx_state_0\/main_1 3.207
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \UART:BUART:sCR_SyncCtl:CtrlReg\ \UART:BUART:sCR_SyncCtl:CtrlReg\/clock \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 0.360
Route 1 \UART:BUART:control_3\ \UART:BUART:sCR_SyncCtl:CtrlReg\/control_3 \UART:BUART:tx_state_0\/main_1 2.847
macrocell30 U(0,0) 1 \UART:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 2.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u0\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/clock \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb 2.060
Route 1 \Counter_Right:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_Down:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Down:CounterUDB:sC16:counterdp:u1\/ci 2.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u0\ \Counter_Down:CounterUDB:sC16:counterdp:u0\/clock \Counter_Down:CounterUDB:sC16:counterdp:u0\/co_msb 2.060
Route 1 \Counter_Down:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Down:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Down:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell8 U(2,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 2.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell9 U(2,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u0\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/clock \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb 2.060
Route 1 \Counter_Left:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell10 U(3,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 2.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell11 U(3,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/clock \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb 2.060
Route 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell12 U(2,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 2.060
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(0,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/clock \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb 2.060
Route 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell14 U(1,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM:PWMUDB:sP16:pwmdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,2) 1 \PWM:PWMUDB:sP16:pwmdp:u0\ \PWM:PWMUDB:sP16:pwmdp:u0\/clock \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb 2.140
Route 1 \PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \PWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell4 U(0,2) 1 \PWM:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.675
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,2) 1 \PWM:PWMUDB:genblk1:ctrlreg\ \PWM:PWMUDB:genblk1:ctrlreg\/clock \PWM:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM:PWMUDB:control_7\ \PWM:PWMUDB:genblk1:ctrlreg\/control_7 \PWM:PWMUDB:runmode_enable\/main_0 2.315
macrocell36 U(2,2) 1 \PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 3.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(3,4) 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/clock_0 \PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM:PWMUDB:prevCompare1\ \PWM:PWMUDB:prevCompare1\/q \PWM:PWMUDB:status_0\/main_0 2.286
macrocell38 U(3,4) 1 \PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\Counter_Down:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Down:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.659
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u1\ \Counter_Down:CounterUDB:sC16:counterdp:u1\/clock \Counter_Down:CounterUDB:sC16:counterdp:u1\/ce0_comb 0.720
Route 1 \Counter_Down:CounterUDB:reload\ \Counter_Down:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Down:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.939
datapathcell7 U(3,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Counter_Down:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Down:CounterUDB:sC16:counterdp:u1\/cs_addr_0 3.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u1\ \Counter_Down:CounterUDB:sC16:counterdp:u1\/clock \Counter_Down:CounterUDB:sC16:counterdp:u1\/ce0_comb 0.720
datapathcell8 U(2,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u1\ \Counter_Down:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Down:CounterUDB:sC16:counterdp:u1\/cs_addr_0 3.059
datapathcell8 U(2,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ CyBUS_CLK
Source Destination Delay (ns)
E1(0)_PAD \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 32.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 E1(0)_PAD E1(0)_PAD E1(0)/pad_in 0.000
iocell4 P0[0] 1 E1(0) E1(0)/pad_in E1(0)/fb 7.922
Route 1 Net_202 E1(0)/fb \Counter_Forward:CounterUDB:count_enable\/main_1 5.314
macrocell25 U(2,3) 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/main_1 \Counter_Forward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Forward:CounterUDB:count_enable\ \Counter_Forward:CounterUDB:count_enable\/q \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 6.689
datapathcell13 U(0,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Forward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Forward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Forward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell14 U(1,3) 1 \Counter_Forward:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Clock path delay 0.000
E5(0)_PAD \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 31.293
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 E5(0)_PAD E5(0)_PAD E5(0)/pad_in 0.000
iocell8 P0[4] 1 E5(0) E5(0)/pad_in E5(0)/fb 7.563
Route 1 Net_314 E5(0)/fb \Counter_Backward:CounterUDB:count_enable\/main_1 6.487
macrocell21 U(2,3) 1 \Counter_Backward:CounterUDB:count_enable\ \Counter_Backward:CounterUDB:count_enable\/main_1 \Counter_Backward:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Backward:CounterUDB:count_enable\ \Counter_Backward:CounterUDB:count_enable\/q \Counter_Backward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 4.533
datapathcell11 U(3,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Backward:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Backward:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Backward:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell12 U(2,4) 1 \Counter_Backward:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Clock path delay 0.000
E4(0)_PAD \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 29.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 E4(0)_PAD E4(0)_PAD E4(0)/pad_in 0.000
iocell7 P0[3] 1 E4(0) E4(0)/pad_in E4(0)/fb 7.958
Route 1 Net_301 E4(0)/fb \Counter_Left:CounterUDB:count_enable\/main_1 6.621
macrocell17 U(2,5) 1 \Counter_Left:CounterUDB:count_enable\ \Counter_Left:CounterUDB:count_enable\/main_1 \Counter_Left:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Left:CounterUDB:count_enable\ \Counter_Left:CounterUDB:count_enable\/q \Counter_Left:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.298
datapathcell9 U(2,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u0\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Left:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Left:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Left:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell10 U(3,5) 1 \Counter_Left:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Clock path delay 0.000
E2(0)_PAD \Counter_Down:CounterUDB:sC16:counterdp:u1\/ci 29.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 E2(0)_PAD E2(0)_PAD E2(0)/pad_in 0.000
iocell5 P0[1] 1 E2(0) E2(0)/pad_in E2(0)/fb 7.962
Route 1 Net_275 E2(0)/fb \Counter_Down:CounterUDB:count_enable\/main_1 5.703
macrocell13 U(2,3) 1 \Counter_Down:CounterUDB:count_enable\ \Counter_Down:CounterUDB:count_enable\/main_1 \Counter_Down:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Down:CounterUDB:count_enable\ \Counter_Down:CounterUDB:count_enable\/q \Counter_Down:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.075
datapathcell7 U(3,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u0\ \Counter_Down:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Down:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Down:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Down:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Down:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell8 U(2,2) 1 \Counter_Down:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Clock path delay 0.000
E3(0)_PAD \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 28.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 E3(0)_PAD E3(0)_PAD E3(0)/pad_in 0.000
iocell6 P0[2] 1 E3(0) E3(0)/pad_in E3(0)/fb 7.950
Route 1 Net_288 E3(0)/fb \Counter_Right:CounterUDB:count_enable\/main_1 5.090
macrocell9 U(3,4) 1 \Counter_Right:CounterUDB:count_enable\ \Counter_Right:CounterUDB:count_enable\/main_1 \Counter_Right:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Right:CounterUDB:count_enable\ \Counter_Right:CounterUDB:count_enable\/q \Counter_Right:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.075
datapathcell5 U(2,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u0\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb 5.130
Route 1 \Counter_Right:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Right:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Right:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Counter_Right:CounterUDB:sC16:counterdp:u1\ SETUP 4.230
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx(0)_PAD 29.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_2/main_0 2.541
macrocell1 U(0,0) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx(0)/pin_input 5.375
iocell1 P12[7] 1 Tx(0) Tx(0)/pin_input Tx(0)/pad_out 16.967
Route 1 Tx(0)_PAD Tx(0)/pad_out Tx(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
Net_455/q Trig(0)_PAD 21.777
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(3,2) 1 Net_455 Net_455/clock_0 Net_455/q 1.250
Route 1 Net_455 Net_455/q Trig(0)/pin_input 5.907
iocell3 P3[0] 1 Trig(0) Trig(0)/pin_input Trig(0)/pad_out 14.620
Route 1 Trig(0)_PAD Trig(0)/pad_out Trig(0)_PAD 0.000
Clock Clock path delay 0.000