# Static Timing Analysis

Project : | Design01
Build Time : | 02/23/18 12:35:12
Device : | CY8C4247LQI-BL483
Temperature : | -40C - 85C
VDDA_1 : | 3.30
VDDA_CTB : | 3.30
VDDD_0 : | 3.30
VDDIO_0 : | 3.30
VDDIO_1 : | 3.30
VDDIO_2 : | 3.30
VDDR_BGLS : | 3.30
VDDR_HF : | 3.30
VDDR_HLS : | 3.30
VDDR_LF : | 3.30
VDDR_SYN : | 3.30
Voltage : | 3.3

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
ADC_intClock(FFB) | ADC_intClock(FFB) | 1.043 MHz | 1.043 MHz | N/A |
CyECO | CyECO | 24.000 MHz | 24.000 MHz | N/A |
CyHFClk | CyHFClk | 24.000 MHz | 24.000 MHz | 30.019 MHz |
UART_SCBCLK | CyHFClk | 1.412 MHz | 1.412 MHz | N/A |
ADC_intClock | CyHFClk | 1.043 MHz | 1.043 MHz | N/A |
SwClk | CyHFClk | 400.000 Hz | 400.000 Hz | 81.546 MHz |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 48.000 MHz | 48.000 MHz | N/A |
CyLFClk | CyLFClk | 32.768 kHz | 32.768 kHz | N/A |
CyRouted1 | CyRouted1 | 24.000 MHz | 24.000 MHz | N/A |
CySysClk | CySysClk | 24.000 MHz | 24.000 MHz | N/A |
CyWCO | CyWCO | 32.768 kHz | 32.768 kHz | N/A |
SwClk(FFB) | SwClk(FFB) | 400.000 Hz | 400.000 Hz | N/A |
UART_SCBCLK(FFB) | UART_SCBCLK(FFB) | 1.412 MHz | 1.412 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : CyHFClk : Positive edge(Required Frequency 24 MHz)
+ Destination Clock : CyHFClk : Positive edge(Required Frequency 24 MHz)
Path Delay Requirement : 41.6667ns(24 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 30.019 MHz | 33.312 | 8.355 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/clock | \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | 3.752
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 31.366 MHz | 31.882 | 9.785 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/clock | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | 3.752
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 32.839 MHz | 30.452 | 11.215 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/clock | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | 3.752
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 32.989 MHz | 30.313 | 11.354 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/clock | \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 | 4.063
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 33.331 MHz | 30.002 | 11.665 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/clock | \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | 3.752
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 34.457 MHz | 29.022 | 12.645 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/clock | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 3.850
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | 3.752
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 34.622 MHz | 28.883 | 12.784 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/clock | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 | 4.063
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 34.999 MHz | 28.572 | 13.095 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/clock | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 1.430
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | 3.752
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 36.426 MHz | 27.453 | 14.214 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/clock | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 | 4.063
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 36.843 MHz | 27.142 | 14.525 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/clock | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | 3.752
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.310
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000

+ Destination Clock : SwClk : Positive edge(Required Frequency 400 Hz)
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFClk

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
SW(0)/fb | \GlitchFilter_1:genblk1[0]:samples_0\/main_0 | 81.546 MHz | 12.263 | 29.404 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell6 | P2[7] | 1 | SW(0) | SW(0)/in_clock | SW(0)/fb | 4.047
Route |  | 1 | Net_557 | SW(0)/fb | \GlitchFilter_1:genblk1[0]:samples_0\/main_0 | 4.706
macrocell10 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
SW(0)/fb | Net_108/main_0 | 81.546 MHz | 12.263 | 29.404 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell6 | P2[7] | 1 | SW(0) | SW(0)/in_clock | SW(0)/fb | 4.047
Route |  | 1 | Net_557 | SW(0)/fb | Net_108/main_0 | 4.706
macrocell11 | U(1,1) | 1 | Net_108 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : SwClk : Positive edge(Required Frequency 400 Hz)
+ Destination Clock : SwClk : Positive edge(Required Frequency 400 Hz)
Path Delay Requirement : 2.5e+006ns(400 Hz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
Net_108/q | Net_1092/clk_en | 109.063 MHz | 9.169 | 2499990.831 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell11 | U(1,1) | 1 | Net_108 | Net_108/clock_0 | Net_108/q | 1.250
Route |  | 1 | Net_108 | Net_108/q | Net_1092/clk_en | 5.819
macrocell12 | U(1,1) | 1 | Net_1092 |  | SETUP | 2.100
Clock |  |  |  |  | Skew | 0.000
Net_108/q | Net_108/main_4 | 109.625 MHz | 9.122 | 2499990.878 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell11 | U(1,1) | 1 | Net_108 | Net_108/clock_0 | Net_108/q | 1.250
macrocell11 | U(1,1) | 1 | Net_108 | Net_108/q | Net_108/main_4 | 4.362
macrocell11 | U(1,1) | 1 | Net_108 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_2\/q | Net_108/main_1 | 141.383 MHz | 7.073 | 2499992.927 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell8 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_2\ | \GlitchFilter_1:genblk1[0]:samples_2\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_2\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_2\ | \GlitchFilter_1:genblk1[0]:samples_2\/q | Net_108/main_1 | 2.313
macrocell11 | U(1,1) | 1 | Net_108 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_0\/q | \GlitchFilter_1:genblk1[0]:samples_1\/main_0 | 141.663 MHz | 7.059 | 2499992.941 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell10 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ | \GlitchFilter_1:genblk1[0]:samples_0\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_0\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ | \GlitchFilter_1:genblk1[0]:samples_0\/q | \GlitchFilter_1:genblk1[0]:samples_1\/main_0 | 2.299
macrocell9 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_0\/q | Net_108/main_3 | 141.663 MHz | 7.059 | 2499992.941 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell10 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ | \GlitchFilter_1:genblk1[0]:samples_0\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_0\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ | \GlitchFilter_1:genblk1[0]:samples_0\/q | Net_108/main_3 | 2.299
macrocell11 | U(1,1) | 1 | Net_108 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_1\/q | \GlitchFilter_1:genblk1[0]:samples_2\/main_0 | 141.703 MHz | 7.057 | 2499992.943 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell9 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_1\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/q | \GlitchFilter_1:genblk1[0]:samples_2\/main_0 | 2.297
macrocell8 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_2\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_1\/q | Net_108/main_2 | 141.703 MHz | 7.057 | 2499992.943 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell9 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_1\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/q | Net_108/main_2 | 2.297
macrocell11 | U(1,1) | 1 | Net_108 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:count_0\/q | Net_1271/main_3 | 142.552 MHz | 7.015 | 2499992.985 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell7 | U(1,0) | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/clock_0 | \FreqDiv_1:count_0\/q | 1.250
Route |  | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/q | Net_1271/main_3 | 2.255
macrocell5 | U(1,0) | 1 | Net_1271 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:count_0\/q | \FreqDiv_1:count_1\/main_1 | 142.552 MHz | 7.015 | 2499992.985 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell7 | U(1,0) | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/clock_0 | \FreqDiv_1:count_0\/q | 1.250
Route |  | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/q | \FreqDiv_1:count_1\/main_1 | 2.255
macrocell6 | U(1,0) | 1 | \FreqDiv_1:count_1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:not_last_reset\/q | Net_1271/main_0 | 142.613 MHz | 7.012 | 2499992.988 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(1,0) | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/clock_0 | \FreqDiv_1:not_last_reset\/q | 1.250
Route |  | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/q | Net_1271/main_0 | 2.252
macrocell5 | U(1,0) | 1 | Net_1271 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : CyHFClk : Positive edge
+ Destination Clock : CyHFClk : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 3.210 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/clock | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 3.210
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 3.210 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/clock | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.210
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 3.210 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/clock | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 3.210
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_1 | 4.940 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_1 | 2.900
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_1 | 4.943 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_1 | 2.903
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_182/main_0 | 4.946 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_182/main_0 | 2.906
macrocell3 | U(0,1) | 1 | Net_182 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 5.830 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/clock | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | 3.210
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | 0.000
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/ci | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 2.620
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 5.830 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(1,1) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/clock | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | 3.210
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | 0.000
datapathcell3 | U(1,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/ci | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | 2.620
Route |  | 1 | \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ | \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb | \Timer_1:TimerUDB:sT32:timerdp:u3\/ci | 0.000
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_0 | 6.111 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/clock | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | 3.270
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ | \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb | \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_0 | 2.841
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_1 | 6.162 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,1) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_1 | 4.122
datapathcell4 | U(0,0) | 1 | \Timer_1:TimerUDB:sT32:timerdp:u3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Destination Clock : SwClk : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
SW(0)/fb | \GlitchFilter_1:genblk1[0]:samples_0\/main_0 | 7.446 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell6 | P2[7] | 1 | SW(0) | SW(0)/in_clock | SW(0)/fb | 2.740
Route |  | 1 | Net_557 | SW(0)/fb | \GlitchFilter_1:genblk1[0]:samples_0\/main_0 | 4.706
macrocell10 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
SW(0)/fb | Net_108/main_0 | 7.446 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
iocell6 | P2[7] | 1 | SW(0) | SW(0)/in_clock | SW(0)/fb | 2.740
Route |  | 1 | Net_557 | SW(0)/fb | Net_108/main_0 | 4.706
macrocell11 | U(1,1) | 1 | Net_108 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Source Clock : SwClk : Positive edge
+ Destination Clock : SwClk : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\FreqDiv_1:count_1\/q | Net_1271/main_2 | 3.496 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell6 | U(1,0) | 1 | \FreqDiv_1:count_1\ | \FreqDiv_1:count_1\/clock_0 | \FreqDiv_1:count_1\/q | 1.250
Route |  | 1 | \FreqDiv_1:count_1\ | \FreqDiv_1:count_1\/q | Net_1271/main_2 | 2.246
macrocell5 | U(1,0) | 1 | Net_1271 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
Net_1271/q | Net_1271/main_1 | 3.499 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell5 | U(1,0) | 1 | Net_1271 | Net_1271/clock_0 | Net_1271/q | 1.250
macrocell5 | U(1,0) | 1 | Net_1271 | Net_1271/q | Net_1271/main_1 | 2.249
macrocell5 | U(1,0) | 1 | Net_1271 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:not_last_reset\/q | Net_1271/main_0 | 3.502 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(1,0) | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/clock_0 | \FreqDiv_1:not_last_reset\/q | 1.250
Route |  | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/q | Net_1271/main_0 | 2.252
macrocell5 | U(1,0) | 1 | Net_1271 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:not_last_reset\/q | \FreqDiv_1:count_1\/main_0 | 3.502 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(1,0) | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/clock_0 | \FreqDiv_1:not_last_reset\/q | 1.250
Route |  | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/q | \FreqDiv_1:count_1\/main_0 | 2.252
macrocell6 | U(1,0) | 1 | \FreqDiv_1:count_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:not_last_reset\/q | \FreqDiv_1:count_0\/main_0 | 3.502 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(1,0) | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/clock_0 | \FreqDiv_1:not_last_reset\/q | 1.250
Route |  | 1 | \FreqDiv_1:not_last_reset\ | \FreqDiv_1:not_last_reset\/q | \FreqDiv_1:count_0\/main_0 | 2.252
macrocell7 | U(1,0) | 1 | \FreqDiv_1:count_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:count_0\/q | Net_1271/main_3 | 3.505 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell7 | U(1,0) | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/clock_0 | \FreqDiv_1:count_0\/q | 1.250
Route |  | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/q | Net_1271/main_3 | 2.255
macrocell5 | U(1,0) | 1 | Net_1271 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\FreqDiv_1:count_0\/q | \FreqDiv_1:count_1\/main_1 | 3.505 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell7 | U(1,0) | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/clock_0 | \FreqDiv_1:count_0\/q | 1.250
Route |  | 1 | \FreqDiv_1:count_0\ | \FreqDiv_1:count_0\/q | \FreqDiv_1:count_1\/main_1 | 2.255
macrocell6 | U(1,0) | 1 | \FreqDiv_1:count_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_1\/q | \GlitchFilter_1:genblk1[0]:samples_2\/main_0 | 3.547 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell9 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_1\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/q | \GlitchFilter_1:genblk1[0]:samples_2\/main_0 | 2.297
macrocell8 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_1\/q | Net_108/main_2 | 3.547 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell9 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_1\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ | \GlitchFilter_1:genblk1[0]:samples_1\/q | Net_108/main_2 | 2.297
macrocell11 | U(1,1) | 1 | Net_108 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\GlitchFilter_1:genblk1[0]:samples_0\/q | \GlitchFilter_1:genblk1[0]:samples_1\/main_0 | 3.549 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell10 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ | \GlitchFilter_1:genblk1[0]:samples_0\/clock_0 | \GlitchFilter_1:genblk1[0]:samples_0\/q | 1.250
Route |  | 1 | \GlitchFilter_1:genblk1[0]:samples_0\ | \GlitchFilter_1:genblk1[0]:samples_0\/q | \GlitchFilter_1:genblk1[0]:samples_1\/main_0 | 2.299
macrocell9 | U(1,1) | 1 | \GlitchFilter_1:genblk1[0]:samples_1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Clock To Output Section
+ SwClk(FFB)

Source | Destination | Delay (ns)
--- | --- | ---
\PWM_RED:cy_m0s8_tcpwm_1\/line | PIN_RED(0)_PAD | 18.775
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
m0s8tcpwmcell | F(TCPWM,0) | 1 | \PWM_RED:cy_m0s8_tcpwm_1\ | \PWM_RED:cy_m0s8_tcpwm_1\/clock | \PWM_RED:cy_m0s8_tcpwm_1\/line | 0.000
Route |  | 1 | Net_1295 | \PWM_RED:cy_m0s8_tcpwm_1\/line | PIN_RED(0)/pin_input | 2.663
iocell3 | P2[6] | 1 | PIN_RED(0) | PIN_RED(0)/pin_input | PIN_RED(0)/pad_out | 16.112
Route |  | 1 | PIN_RED(0)_PAD | PIN_RED(0)/pad_out | PIN_RED(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000
\PWM_BLUE:cy_m0s8_tcpwm_1\/line_compl | PIN_BLUE(0)_PAD | 15.667
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
m0s8tcpwmcell | F(TCPWM,3) | 1 | \PWM_BLUE:cy_m0s8_tcpwm_1\ | \PWM_BLUE:cy_m0s8_tcpwm_1\/clock | \PWM_BLUE:cy_m0s8_tcpwm_1\/line_compl | 0.000
Route |  | 1 | Net_1289 | \PWM_BLUE:cy_m0s8_tcpwm_1\/line_compl | PIN_BLUE(0)/pin_input | 1.000
iocell5 | P3[7] | 1 | PIN_BLUE(0) | PIN_BLUE(0)/pin_input | PIN_BLUE(0)/pad_out | 14.667
Route |  | 1 | PIN_BLUE(0)_PAD | PIN_BLUE(0)/pad_out | PIN_BLUE(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000

+ Asynchronous Constraints
+ Recovery
+ Source Clock : SwClk : Positive edge(Required Frequency 400 Hz)
+ Destination Clock : SwClk : Positive edge(Required Frequency 400 Hz)
Path Delay Requirement : 2.5e+006ns(400 Hz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\FiltReset:Sync:ctrl_reg\/control_0 | Net_1092/ar_0 | 205.381 MHz | 4.869 | 2499995.131 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell2 | U(1,1) | 1 | \FiltReset:Sync:ctrl_reg\ | \FiltReset:Sync:ctrl_reg\/clock | \FiltReset:Sync:ctrl_reg\/control_0 | 2.580
Route |  | 1 | Net_1170 | \FiltReset:Sync:ctrl_reg\/control_0 | Net_1092/ar_0 | 2.289
macrocell12 | U(1,1) | 1 | Net_1092 |  | RECOVERY | -0.000
Clock |  |  |  |  | Skew | 0.000

+ Removal
+ Source Clock : SwClk : Positive edge
+ Destination Clock : SwClk : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\FiltReset:Sync:ctrl_reg\/control_0 | Net_1092/ar_0 | 4.329 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell2 | U(1,1) | 1 | \FiltReset:Sync:ctrl_reg\ | \FiltReset:Sync:ctrl_reg\/clock | \FiltReset:Sync:ctrl_reg\/control_0 | 2.040
Route |  | 1 | Net_1170 | \FiltReset:Sync:ctrl_reg\/control_0 | Net_1092/ar_0 | 2.289
macrocell12 | U(1,1) | 1 | Net_1092 |  | REMOVAL | 0.000
Clock |  |  |  |  | Skew | 0.000