;
; File Name: cyfitteriar.inc
; 
; PSoC Creator  4.1 Update 1
;
; Description:
; 
;
;-------------------------------------------------------------------------------
; Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
; You may use this file only in accordance with the license, terms, conditions, 
; disclaimers, and limitations in the end user license agreement accompanying 
; the software package with which this file was provided.
;-------------------------------------------------------------------------------

#ifndef INCLUDED_CYFITTERIAR_INC
#define INCLUDED_CYFITTERIAR_INC
    INCLUDE cydeviceiar_trm.inc

/* ADC */
ADC_cy_psoc4_sar__CLOCK_DIV_ID EQU 0x00000041
ADC_cy_psoc4_sar__SAR_ANA_TRIM EQU CYREG_SAR_ANA_TRIM
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 EQU CYREG_SAR_CHAN_CONFIG0
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 EQU CYREG_SAR_CHAN_CONFIG1
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 EQU CYREG_SAR_CHAN_CONFIG2
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 EQU CYREG_SAR_CHAN_CONFIG3
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 EQU CYREG_SAR_CHAN_CONFIG4
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 EQU CYREG_SAR_CHAN_CONFIG5
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 EQU CYREG_SAR_CHAN_CONFIG6
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 EQU CYREG_SAR_CHAN_CONFIG7
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG08 EQU CYREG_SAR_CHAN_CONFIG8
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG09 EQU CYREG_SAR_CHAN_CONFIG9
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG10 EQU CYREG_SAR_CHAN_CONFIG10
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG11 EQU CYREG_SAR_CHAN_CONFIG11
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG12 EQU CYREG_SAR_CHAN_CONFIG12
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG13 EQU CYREG_SAR_CHAN_CONFIG13
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG14 EQU CYREG_SAR_CHAN_CONFIG14
ADC_cy_psoc4_sar__SAR_CHAN_CONFIG15 EQU CYREG_SAR_CHAN_CONFIG15
ADC_cy_psoc4_sar__SAR_CHAN_EN EQU CYREG_SAR_CHAN_EN
ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID EQU CYREG_SAR_CHAN_RESULT_VALID
ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 EQU CYREG_SAR_CHAN_RESULT0
ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 EQU CYREG_SAR_CHAN_RESULT1
ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 EQU CYREG_SAR_CHAN_RESULT2
ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 EQU CYREG_SAR_CHAN_RESULT3
ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 EQU CYREG_SAR_CHAN_RESULT4
ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 EQU CYREG_SAR_CHAN_RESULT5
ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 EQU CYREG_SAR_CHAN_RESULT6
ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 EQU CYREG_SAR_CHAN_RESULT7
ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 EQU CYREG_SAR_CHAN_RESULT8
ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 EQU CYREG_SAR_CHAN_RESULT9
ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 EQU CYREG_SAR_CHAN_RESULT10
ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 EQU CYREG_SAR_CHAN_RESULT11
ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 EQU CYREG_SAR_CHAN_RESULT12
ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 EQU CYREG_SAR_CHAN_RESULT13
ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 EQU CYREG_SAR_CHAN_RESULT14
ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 EQU CYREG_SAR_CHAN_RESULT15
ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID EQU CYREG_SAR_CHAN_WORK_VALID
ADC_cy_psoc4_sar__SAR_CHAN_WORK00 EQU CYREG_SAR_CHAN_WORK0
ADC_cy_psoc4_sar__SAR_CHAN_WORK01 EQU CYREG_SAR_CHAN_WORK1
ADC_cy_psoc4_sar__SAR_CHAN_WORK02 EQU CYREG_SAR_CHAN_WORK2
ADC_cy_psoc4_sar__SAR_CHAN_WORK03 EQU CYREG_SAR_CHAN_WORK3
ADC_cy_psoc4_sar__SAR_CHAN_WORK04 EQU CYREG_SAR_CHAN_WORK4
ADC_cy_psoc4_sar__SAR_CHAN_WORK05 EQU CYREG_SAR_CHAN_WORK5
ADC_cy_psoc4_sar__SAR_CHAN_WORK06 EQU CYREG_SAR_CHAN_WORK6
ADC_cy_psoc4_sar__SAR_CHAN_WORK07 EQU CYREG_SAR_CHAN_WORK7
ADC_cy_psoc4_sar__SAR_CHAN_WORK08 EQU CYREG_SAR_CHAN_WORK8
ADC_cy_psoc4_sar__SAR_CHAN_WORK09 EQU CYREG_SAR_CHAN_WORK9
ADC_cy_psoc4_sar__SAR_CHAN_WORK10 EQU CYREG_SAR_CHAN_WORK10
ADC_cy_psoc4_sar__SAR_CHAN_WORK11 EQU CYREG_SAR_CHAN_WORK11
ADC_cy_psoc4_sar__SAR_CHAN_WORK12 EQU CYREG_SAR_CHAN_WORK12
ADC_cy_psoc4_sar__SAR_CHAN_WORK13 EQU CYREG_SAR_CHAN_WORK13
ADC_cy_psoc4_sar__SAR_CHAN_WORK14 EQU CYREG_SAR_CHAN_WORK14
ADC_cy_psoc4_sar__SAR_CHAN_WORK15 EQU CYREG_SAR_CHAN_WORK15
ADC_cy_psoc4_sar__SAR_CTRL EQU CYREG_SAR_CTRL
ADC_cy_psoc4_sar__SAR_DFT_CTRL EQU CYREG_SAR_DFT_CTRL
ADC_cy_psoc4_sar__SAR_INTR EQU CYREG_SAR_INTR
ADC_cy_psoc4_sar__SAR_INTR_CAUSE EQU CYREG_SAR_INTR_CAUSE
ADC_cy_psoc4_sar__SAR_INTR_MASK EQU CYREG_SAR_INTR_MASK
ADC_cy_psoc4_sar__SAR_INTR_MASKED EQU CYREG_SAR_INTR_MASKED
ADC_cy_psoc4_sar__SAR_INTR_SET EQU CYREG_SAR_INTR_SET
ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL EQU CYREG_SAR_MUX_SWITCH_HW_CTRL
ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 EQU CYREG_SAR_MUX_SWITCH0
ADC_cy_psoc4_sar__SAR_NUMBER EQU 0
ADC_cy_psoc4_sar__SAR_PUMP_CTRL EQU CYREG_SAR_PUMP_CTRL
ADC_cy_psoc4_sar__SAR_RANGE_COND EQU CYREG_SAR_RANGE_COND
ADC_cy_psoc4_sar__SAR_RANGE_INTR EQU CYREG_SAR_RANGE_INTR
ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK EQU CYREG_SAR_RANGE_INTR_MASK
ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED EQU CYREG_SAR_RANGE_INTR_MASKED
ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET EQU CYREG_SAR_RANGE_INTR_SET
ADC_cy_psoc4_sar__SAR_RANGE_THRES EQU CYREG_SAR_RANGE_THRES
ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL EQU CYREG_SAR_SAMPLE_CTRL
ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 EQU CYREG_SAR_SAMPLE_TIME01
ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 EQU CYREG_SAR_SAMPLE_TIME23
ADC_cy_psoc4_sar__SAR_SATURATE_INTR EQU CYREG_SAR_SATURATE_INTR
ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK EQU CYREG_SAR_SATURATE_INTR_MASK
ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED EQU CYREG_SAR_SATURATE_INTR_MASKED
ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET EQU CYREG_SAR_SATURATE_INTR_SET
ADC_cy_psoc4_sar__SAR_START_CTRL EQU CYREG_SAR_START_CTRL
ADC_cy_psoc4_sar__SAR_STATUS EQU CYREG_SAR_STATUS
ADC_cy_psoc4_sar__SAR_WOUNDING EQU CYREG_SAR_WOUNDING
ADC_intClock__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL6
ADC_intClock__DIV_ID EQU 0x00000041
ADC_intClock__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL1
ADC_intClock__PA_DIV_ID EQU 0x000000FF
ADC_IRQ__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
ADC_IRQ__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
ADC_IRQ__INTC_MASK EQU 0x8000
ADC_IRQ__INTC_NUMBER EQU 15
ADC_IRQ__INTC_PRIOR_MASK EQU 0xC0000000
ADC_IRQ__INTC_PRIOR_NUM EQU 3
ADC_IRQ__INTC_PRIOR_REG EQU CYREG_CM0_IPR3
ADC_IRQ__INTC_SET_EN_REG EQU CYREG_CM0_ISER
ADC_IRQ__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* FiltInt */
FiltInt__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
FiltInt__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
FiltInt__INTC_MASK EQU 0x02
FiltInt__INTC_NUMBER EQU 1
FiltInt__INTC_PRIOR_MASK EQU 0xC000
FiltInt__INTC_PRIOR_NUM EQU 3
FiltInt__INTC_PRIOR_REG EQU CYREG_CM0_IPR0
FiltInt__INTC_SET_EN_REG EQU CYREG_CM0_ISER
FiltInt__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* FiltReset */
FiltReset_Sync_ctrl_reg__0__MASK EQU 0x01
FiltReset_Sync_ctrl_reg__0__POS EQU 0
FiltReset_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_UDB_W16_ACTL1
FiltReset_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_UDB_W16_CTL1
FiltReset_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_UDB_W16_CTL1
FiltReset_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_UDB_W16_CTL1
FiltReset_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_UDB_W16_CTL1
FiltReset_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_UDB_W16_MSK1
FiltReset_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_UDB_W16_MSK1
FiltReset_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_UDB_W16_MSK1
FiltReset_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_UDB_W16_MSK1
FiltReset_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL1
FiltReset_Sync_ctrl_reg__CONTROL_REG EQU CYREG_UDB_W8_CTL1
FiltReset_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_UDB_CAT16_CTL_ST1
FiltReset_Sync_ctrl_reg__COUNT_REG EQU CYREG_UDB_W8_CTL1
FiltReset_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_UDB_CAT16_CTL_ST1
FiltReset_Sync_ctrl_reg__MASK EQU 0x01
FiltReset_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK1
FiltReset_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK1
FiltReset_Sync_ctrl_reg__PERIOD_REG EQU CYREG_UDB_W8_MSK1

/* IDAC */
IDAC_cy_psoc4_idac__CONTROL EQU CYREG_CSD_CONFIG
IDAC_cy_psoc4_idac__CSD_IDAC EQU CYREG_CSD_IDAC
IDAC_cy_psoc4_idac__CSD_IDAC_SHIFT EQU 0
IDAC_cy_psoc4_idac__CSD_TRIM1 EQU CYREG_CSD_TRIM1
IDAC_cy_psoc4_idac__CSD_TRIM1_SHIFT EQU 0
IDAC_cy_psoc4_idac__CSD_TRIM2 EQU CYREG_CSD_TRIM2
IDAC_cy_psoc4_idac__CSD_TRIM2_SHIFT EQU 0
IDAC_cy_psoc4_idac__IDAC_NUMBER EQU 1
IDAC_cy_psoc4_idac__POLARITY EQU CYREG_CSD_CONFIG
IDAC_cy_psoc4_idac__POLARITY_SHIFT EQU 16

/* PIN_BLUE */
PIN_BLUE__0__DR EQU CYREG_GPIO_PRT3_DR
PIN_BLUE__0__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
PIN_BLUE__0__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
PIN_BLUE__0__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
PIN_BLUE__0__HSIOM EQU CYREG_HSIOM_PORT_SEL3
PIN_BLUE__0__HSIOM_MASK EQU 0xF0000000
PIN_BLUE__0__HSIOM_SHIFT EQU 28
PIN_BLUE__0__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
PIN_BLUE__0__INTR EQU CYREG_GPIO_PRT3_INTR
PIN_BLUE__0__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
PIN_BLUE__0__INTSTAT EQU CYREG_GPIO_PRT3_INTR
PIN_BLUE__0__MASK EQU 0x80
PIN_BLUE__0__OUT_SEL EQU CYREG_UDB_PA3_CFG10
PIN_BLUE__0__OUT_SEL_SHIFT EQU 14
PIN_BLUE__0__OUT_SEL_VAL EQU -1
PIN_BLUE__0__PA__CFG0 EQU CYREG_UDB_PA3_CFG0
PIN_BLUE__0__PA__CFG1 EQU CYREG_UDB_PA3_CFG1
PIN_BLUE__0__PA__CFG10 EQU CYREG_UDB_PA3_CFG10
PIN_BLUE__0__PA__CFG11 EQU CYREG_UDB_PA3_CFG11
PIN_BLUE__0__PA__CFG12 EQU CYREG_UDB_PA3_CFG12
PIN_BLUE__0__PA__CFG13 EQU CYREG_UDB_PA3_CFG13
PIN_BLUE__0__PA__CFG14 EQU CYREG_UDB_PA3_CFG14
PIN_BLUE__0__PA__CFG2 EQU CYREG_UDB_PA3_CFG2
PIN_BLUE__0__PA__CFG3 EQU CYREG_UDB_PA3_CFG3
PIN_BLUE__0__PA__CFG4 EQU CYREG_UDB_PA3_CFG4
PIN_BLUE__0__PA__CFG5 EQU CYREG_UDB_PA3_CFG5
PIN_BLUE__0__PA__CFG6 EQU CYREG_UDB_PA3_CFG6
PIN_BLUE__0__PA__CFG7 EQU CYREG_UDB_PA3_CFG7
PIN_BLUE__0__PA__CFG8 EQU CYREG_UDB_PA3_CFG8
PIN_BLUE__0__PA__CFG9 EQU CYREG_UDB_PA3_CFG9
PIN_BLUE__0__PC EQU CYREG_GPIO_PRT3_PC
PIN_BLUE__0__PC2 EQU CYREG_GPIO_PRT3_PC2
PIN_BLUE__0__PORT EQU 3
PIN_BLUE__0__PS EQU CYREG_GPIO_PRT3_PS
PIN_BLUE__0__SHIFT EQU 7
PIN_BLUE__DR EQU CYREG_GPIO_PRT3_DR
PIN_BLUE__DR_CLR EQU CYREG_GPIO_PRT3_DR_CLR
PIN_BLUE__DR_INV EQU CYREG_GPIO_PRT3_DR_INV
PIN_BLUE__DR_SET EQU CYREG_GPIO_PRT3_DR_SET
PIN_BLUE__INTCFG EQU CYREG_GPIO_PRT3_INTR_CFG
PIN_BLUE__INTR EQU CYREG_GPIO_PRT3_INTR
PIN_BLUE__INTR_CFG EQU CYREG_GPIO_PRT3_INTR_CFG
PIN_BLUE__INTSTAT EQU CYREG_GPIO_PRT3_INTR
PIN_BLUE__MASK EQU 0x80
PIN_BLUE__PA__CFG0 EQU CYREG_UDB_PA3_CFG0
PIN_BLUE__PA__CFG1 EQU CYREG_UDB_PA3_CFG1
PIN_BLUE__PA__CFG10 EQU CYREG_UDB_PA3_CFG10
PIN_BLUE__PA__CFG11 EQU CYREG_UDB_PA3_CFG11
PIN_BLUE__PA__CFG12 EQU CYREG_UDB_PA3_CFG12
PIN_BLUE__PA__CFG13 EQU CYREG_UDB_PA3_CFG13
PIN_BLUE__PA__CFG14 EQU CYREG_UDB_PA3_CFG14
PIN_BLUE__PA__CFG2 EQU CYREG_UDB_PA3_CFG2
PIN_BLUE__PA__CFG3 EQU CYREG_UDB_PA3_CFG3
PIN_BLUE__PA__CFG4 EQU CYREG_UDB_PA3_CFG4
PIN_BLUE__PA__CFG5 EQU CYREG_UDB_PA3_CFG5
PIN_BLUE__PA__CFG6 EQU CYREG_UDB_PA3_CFG6
PIN_BLUE__PA__CFG7 EQU CYREG_UDB_PA3_CFG7
PIN_BLUE__PA__CFG8 EQU CYREG_UDB_PA3_CFG8
PIN_BLUE__PA__CFG9 EQU CYREG_UDB_PA3_CFG9
PIN_BLUE__PC EQU CYREG_GPIO_PRT3_PC
PIN_BLUE__PC2 EQU CYREG_GPIO_PRT3_PC2
PIN_BLUE__PORT EQU 3
PIN_BLUE__PS EQU CYREG_GPIO_PRT3_PS
PIN_BLUE__SHIFT EQU 7

/* PIN_RED */
PIN_RED__0__DR EQU CYREG_GPIO_PRT2_DR
PIN_RED__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
PIN_RED__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
PIN_RED__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
PIN_RED__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
PIN_RED__0__HSIOM_MASK EQU 0x0F000000
PIN_RED__0__HSIOM_SHIFT EQU 24
PIN_RED__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
PIN_RED__0__INTR EQU CYREG_GPIO_PRT2_INTR
PIN_RED__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
PIN_RED__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
PIN_RED__0__MASK EQU 0x40
PIN_RED__0__OUT_SEL EQU CYREG_UDB_PA2_CFG10
PIN_RED__0__OUT_SEL_SHIFT EQU 12
PIN_RED__0__OUT_SEL_VAL EQU 1
PIN_RED__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
PIN_RED__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
PIN_RED__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
PIN_RED__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
PIN_RED__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
PIN_RED__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
PIN_RED__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
PIN_RED__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
PIN_RED__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
PIN_RED__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
PIN_RED__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
PIN_RED__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
PIN_RED__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
PIN_RED__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
PIN_RED__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
PIN_RED__0__PC EQU CYREG_GPIO_PRT2_PC
PIN_RED__0__PC2 EQU CYREG_GPIO_PRT2_PC2
PIN_RED__0__PORT EQU 2
PIN_RED__0__PS EQU CYREG_GPIO_PRT2_PS
PIN_RED__0__SHIFT EQU 6
PIN_RED__DR EQU CYREG_GPIO_PRT2_DR
PIN_RED__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
PIN_RED__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
PIN_RED__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
PIN_RED__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
PIN_RED__INTR EQU CYREG_GPIO_PRT2_INTR
PIN_RED__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
PIN_RED__INTSTAT EQU CYREG_GPIO_PRT2_INTR
PIN_RED__MASK EQU 0x40
PIN_RED__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
PIN_RED__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
PIN_RED__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
PIN_RED__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
PIN_RED__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
PIN_RED__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
PIN_RED__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
PIN_RED__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
PIN_RED__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
PIN_RED__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
PIN_RED__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
PIN_RED__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
PIN_RED__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
PIN_RED__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
PIN_RED__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
PIN_RED__PC EQU CYREG_GPIO_PRT2_PC
PIN_RED__PC2 EQU CYREG_GPIO_PRT2_PC2
PIN_RED__PORT EQU 2
PIN_RED__PS EQU CYREG_GPIO_PRT2_PS
PIN_RED__SHIFT EQU 6

/* PWM_BLUE */
PWM_BLUE_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT3_CC
PWM_BLUE_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT3_CC_BUFF
PWM_BLUE_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT3_COUNTER
PWM_BLUE_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT3_CTRL
PWM_BLUE_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT3_INTR
PWM_BLUE_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT3_INTR_MASK
PWM_BLUE_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT3_INTR_MASKED
PWM_BLUE_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT3_INTR_SET
PWM_BLUE_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT3_PERIOD
PWM_BLUE_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT3_PERIOD_BUFF
PWM_BLUE_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT3_STATUS
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x08
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 3
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x800
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 11
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x8000000
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 27
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x80000
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 19
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x08
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 3
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x08
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 3
PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 3
PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT3_TR_CTRL0
PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT3_TR_CTRL1
PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT3_TR_CTRL2

/* PWM_RED */
PWM_RED_cy_m0s8_tcpwm_1__CC EQU CYREG_TCPWM_CNT0_CC
PWM_RED_cy_m0s8_tcpwm_1__CC_BUFF EQU CYREG_TCPWM_CNT0_CC_BUFF
PWM_RED_cy_m0s8_tcpwm_1__COUNTER EQU CYREG_TCPWM_CNT0_COUNTER
PWM_RED_cy_m0s8_tcpwm_1__CTRL EQU CYREG_TCPWM_CNT0_CTRL
PWM_RED_cy_m0s8_tcpwm_1__INTR EQU CYREG_TCPWM_CNT0_INTR
PWM_RED_cy_m0s8_tcpwm_1__INTR_MASK EQU CYREG_TCPWM_CNT0_INTR_MASK
PWM_RED_cy_m0s8_tcpwm_1__INTR_MASKED EQU CYREG_TCPWM_CNT0_INTR_MASKED
PWM_RED_cy_m0s8_tcpwm_1__INTR_SET EQU CYREG_TCPWM_CNT0_INTR_SET
PWM_RED_cy_m0s8_tcpwm_1__PERIOD EQU CYREG_TCPWM_CNT0_PERIOD
PWM_RED_cy_m0s8_tcpwm_1__PERIOD_BUFF EQU CYREG_TCPWM_CNT0_PERIOD_BUFF
PWM_RED_cy_m0s8_tcpwm_1__STATUS EQU CYREG_TCPWM_CNT0_STATUS
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMD EQU CYREG_TCPWM_CMD
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK EQU 0x01
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT EQU 0
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK EQU 0x100
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT EQU 8
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK EQU 0x1000000
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT EQU 24
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK EQU 0x10000
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT EQU 16
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL EQU CYREG_TCPWM_CTRL
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK EQU 0x01
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT EQU 0
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE EQU CYREG_TCPWM_INTR_CAUSE
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK EQU 0x01
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT EQU 0
PWM_RED_cy_m0s8_tcpwm_1__TCPWM_NUMBER EQU 0
PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL0 EQU CYREG_TCPWM_CNT0_TR_CTRL0
PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL1 EQU CYREG_TCPWM_CNT0_TR_CTRL1
PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL2 EQU CYREG_TCPWM_CNT0_TR_CTRL2

/* SENSOR_1 */
SENSOR_1__0__DR EQU CYREG_GPIO_PRT0_DR
SENSOR_1__0__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
SENSOR_1__0__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
SENSOR_1__0__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
SENSOR_1__0__HSIOM EQU CYREG_HSIOM_PORT_SEL0
SENSOR_1__0__HSIOM_MASK EQU 0x00F00000
SENSOR_1__0__HSIOM_SHIFT EQU 20
SENSOR_1__0__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
SENSOR_1__0__INTR EQU CYREG_GPIO_PRT0_INTR
SENSOR_1__0__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
SENSOR_1__0__INTSTAT EQU CYREG_GPIO_PRT0_INTR
SENSOR_1__0__MASK EQU 0x20
SENSOR_1__0__OUT_SEL EQU CYREG_UDB_PA0_CFG10
SENSOR_1__0__OUT_SEL_SHIFT EQU 10
SENSOR_1__0__OUT_SEL_VAL EQU 0
SENSOR_1__0__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
SENSOR_1__0__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
SENSOR_1__0__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
SENSOR_1__0__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
SENSOR_1__0__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
SENSOR_1__0__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
SENSOR_1__0__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
SENSOR_1__0__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
SENSOR_1__0__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
SENSOR_1__0__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
SENSOR_1__0__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
SENSOR_1__0__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
SENSOR_1__0__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
SENSOR_1__0__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
SENSOR_1__0__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
SENSOR_1__0__PC EQU CYREG_GPIO_PRT0_PC
SENSOR_1__0__PC2 EQU CYREG_GPIO_PRT0_PC2
SENSOR_1__0__PORT EQU 0
SENSOR_1__0__PS EQU CYREG_GPIO_PRT0_PS
SENSOR_1__0__SHIFT EQU 5
SENSOR_1__DR EQU CYREG_GPIO_PRT0_DR
SENSOR_1__DR_CLR EQU CYREG_GPIO_PRT0_DR_CLR
SENSOR_1__DR_INV EQU CYREG_GPIO_PRT0_DR_INV
SENSOR_1__DR_SET EQU CYREG_GPIO_PRT0_DR_SET
SENSOR_1__INTCFG EQU CYREG_GPIO_PRT0_INTR_CFG
SENSOR_1__INTR EQU CYREG_GPIO_PRT0_INTR
SENSOR_1__INTR_CFG EQU CYREG_GPIO_PRT0_INTR_CFG
SENSOR_1__INTSTAT EQU CYREG_GPIO_PRT0_INTR
SENSOR_1__MASK EQU 0x20
SENSOR_1__PA__CFG0 EQU CYREG_UDB_PA0_CFG0
SENSOR_1__PA__CFG1 EQU CYREG_UDB_PA0_CFG1
SENSOR_1__PA__CFG10 EQU CYREG_UDB_PA0_CFG10
SENSOR_1__PA__CFG11 EQU CYREG_UDB_PA0_CFG11
SENSOR_1__PA__CFG12 EQU CYREG_UDB_PA0_CFG12
SENSOR_1__PA__CFG13 EQU CYREG_UDB_PA0_CFG13
SENSOR_1__PA__CFG14 EQU CYREG_UDB_PA0_CFG14
SENSOR_1__PA__CFG2 EQU CYREG_UDB_PA0_CFG2
SENSOR_1__PA__CFG3 EQU CYREG_UDB_PA0_CFG3
SENSOR_1__PA__CFG4 EQU CYREG_UDB_PA0_CFG4
SENSOR_1__PA__CFG5 EQU CYREG_UDB_PA0_CFG5
SENSOR_1__PA__CFG6 EQU CYREG_UDB_PA0_CFG6
SENSOR_1__PA__CFG7 EQU CYREG_UDB_PA0_CFG7
SENSOR_1__PA__CFG8 EQU CYREG_UDB_PA0_CFG8
SENSOR_1__PA__CFG9 EQU CYREG_UDB_PA0_CFG9
SENSOR_1__PC EQU CYREG_GPIO_PRT0_PC
SENSOR_1__PC2 EQU CYREG_GPIO_PRT0_PC2
SENSOR_1__PORT EQU 0
SENSOR_1__PS EQU CYREG_GPIO_PRT0_PS
SENSOR_1__SHIFT EQU 5

/* SENSOR_2 */
SENSOR_2__0__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_2__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_2__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_2__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_2__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
SENSOR_2__0__HSIOM_MASK EQU 0x0000000F
SENSOR_2__0__HSIOM_SHIFT EQU 0
SENSOR_2__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_2__0__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_2__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_2__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_2__0__MASK EQU 0x01
SENSOR_2__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
SENSOR_2__0__OUT_SEL_SHIFT EQU 0
SENSOR_2__0__OUT_SEL_VAL EQU 3
SENSOR_2__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_2__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_2__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_2__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_2__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_2__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_2__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_2__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_2__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_2__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_2__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_2__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_2__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_2__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_2__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_2__0__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_2__0__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_2__0__PORT EQU 1
SENSOR_2__0__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_2__0__SHIFT EQU 0
SENSOR_2__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_2__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_2__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_2__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_2__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_2__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_2__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_2__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_2__MASK EQU 0x01
SENSOR_2__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_2__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_2__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_2__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_2__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_2__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_2__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_2__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_2__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_2__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_2__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_2__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_2__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_2__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_2__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_2__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_2__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_2__PORT EQU 1
SENSOR_2__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_2__SHIFT EQU 0

/* SENSOR_3 */
SENSOR_3__0__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_3__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_3__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_3__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_3__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
SENSOR_3__0__HSIOM_MASK EQU 0x000000F0
SENSOR_3__0__HSIOM_SHIFT EQU 4
SENSOR_3__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_3__0__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_3__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_3__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_3__0__MASK EQU 0x02
SENSOR_3__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
SENSOR_3__0__OUT_SEL_SHIFT EQU 2
SENSOR_3__0__OUT_SEL_VAL EQU 3
SENSOR_3__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_3__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_3__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_3__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_3__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_3__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_3__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_3__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_3__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_3__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_3__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_3__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_3__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_3__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_3__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_3__0__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_3__0__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_3__0__PORT EQU 1
SENSOR_3__0__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_3__0__SHIFT EQU 1
SENSOR_3__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_3__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_3__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_3__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_3__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_3__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_3__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_3__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_3__MASK EQU 0x02
SENSOR_3__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_3__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_3__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_3__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_3__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_3__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_3__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_3__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_3__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_3__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_3__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_3__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_3__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_3__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_3__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_3__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_3__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_3__PORT EQU 1
SENSOR_3__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_3__SHIFT EQU 1

/* SENSOR_4 */
SENSOR_4__0__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_4__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_4__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_4__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_4__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
SENSOR_4__0__HSIOM_MASK EQU 0x00000F00
SENSOR_4__0__HSIOM_SHIFT EQU 8
SENSOR_4__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_4__0__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_4__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_4__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_4__0__MASK EQU 0x04
SENSOR_4__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
SENSOR_4__0__OUT_SEL_SHIFT EQU 4
SENSOR_4__0__OUT_SEL_VAL EQU 3
SENSOR_4__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_4__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_4__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_4__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_4__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_4__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_4__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_4__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_4__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_4__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_4__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_4__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_4__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_4__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_4__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_4__0__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_4__0__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_4__0__PORT EQU 1
SENSOR_4__0__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_4__0__SHIFT EQU 2
SENSOR_4__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_4__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_4__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_4__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_4__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_4__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_4__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_4__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_4__MASK EQU 0x04
SENSOR_4__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_4__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_4__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_4__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_4__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_4__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_4__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_4__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_4__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_4__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_4__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_4__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_4__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_4__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_4__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_4__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_4__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_4__PORT EQU 1
SENSOR_4__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_4__SHIFT EQU 2

/* SENSOR_5 */
SENSOR_5__0__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_5__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_5__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_5__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_5__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
SENSOR_5__0__HSIOM_MASK EQU 0x0000F000
SENSOR_5__0__HSIOM_SHIFT EQU 12
SENSOR_5__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_5__0__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_5__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_5__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_5__0__MASK EQU 0x08
SENSOR_5__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
SENSOR_5__0__OUT_SEL_SHIFT EQU 6
SENSOR_5__0__OUT_SEL_VAL EQU 3
SENSOR_5__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_5__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_5__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_5__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_5__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_5__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_5__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_5__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_5__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_5__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_5__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_5__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_5__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_5__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_5__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_5__0__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_5__0__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_5__0__PORT EQU 1
SENSOR_5__0__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_5__0__SHIFT EQU 3
SENSOR_5__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_5__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_5__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_5__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_5__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_5__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_5__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_5__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_5__MASK EQU 0x08
SENSOR_5__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_5__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_5__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_5__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_5__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_5__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_5__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_5__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_5__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_5__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_5__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_5__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_5__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_5__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_5__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_5__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_5__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_5__PORT EQU 1
SENSOR_5__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_5__SHIFT EQU 3

/* SENSOR_6 */
SENSOR_6__0__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_6__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_6__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_6__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_6__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
SENSOR_6__0__HSIOM_MASK EQU 0xF0000000
SENSOR_6__0__HSIOM_SHIFT EQU 28
SENSOR_6__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_6__0__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_6__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_6__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_6__0__MASK EQU 0x80
SENSOR_6__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
SENSOR_6__0__OUT_SEL_SHIFT EQU 14
SENSOR_6__0__OUT_SEL_VAL EQU 0
SENSOR_6__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_6__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_6__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_6__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_6__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_6__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_6__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_6__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_6__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_6__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_6__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_6__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_6__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_6__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_6__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_6__0__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_6__0__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_6__0__PORT EQU 1
SENSOR_6__0__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_6__0__SHIFT EQU 7
SENSOR_6__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_6__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_6__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_6__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_6__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_6__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_6__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_6__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_6__MASK EQU 0x80
SENSOR_6__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_6__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_6__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_6__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_6__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_6__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_6__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_6__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_6__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_6__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_6__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_6__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_6__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_6__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_6__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_6__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_6__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_6__PORT EQU 1
SENSOR_6__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_6__SHIFT EQU 7

/* SENSOR_7 */
SENSOR_7__0__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_7__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_7__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_7__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_7__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
SENSOR_7__0__HSIOM_MASK EQU 0x0F000000
SENSOR_7__0__HSIOM_SHIFT EQU 24
SENSOR_7__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_7__0__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_7__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_7__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_7__0__MASK EQU 0x40
SENSOR_7__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
SENSOR_7__0__OUT_SEL_SHIFT EQU 12
SENSOR_7__0__OUT_SEL_VAL EQU 0
SENSOR_7__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_7__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_7__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_7__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_7__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_7__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_7__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_7__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_7__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_7__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_7__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_7__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_7__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_7__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_7__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_7__0__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_7__0__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_7__0__PORT EQU 1
SENSOR_7__0__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_7__0__SHIFT EQU 6
SENSOR_7__DR EQU CYREG_GPIO_PRT1_DR
SENSOR_7__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
SENSOR_7__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
SENSOR_7__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
SENSOR_7__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_7__INTR EQU CYREG_GPIO_PRT1_INTR
SENSOR_7__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
SENSOR_7__INTSTAT EQU CYREG_GPIO_PRT1_INTR
SENSOR_7__MASK EQU 0x40
SENSOR_7__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
SENSOR_7__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
SENSOR_7__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
SENSOR_7__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
SENSOR_7__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
SENSOR_7__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
SENSOR_7__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
SENSOR_7__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
SENSOR_7__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
SENSOR_7__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
SENSOR_7__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
SENSOR_7__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
SENSOR_7__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
SENSOR_7__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
SENSOR_7__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
SENSOR_7__PC EQU CYREG_GPIO_PRT1_PC
SENSOR_7__PC2 EQU CYREG_GPIO_PRT1_PC2
SENSOR_7__PORT EQU 1
SENSOR_7__PS EQU CYREG_GPIO_PRT1_PS
SENSOR_7__SHIFT EQU 6

/* SENSOR_8 */
SENSOR_8__0__DR EQU CYREG_GPIO_PRT2_DR
SENSOR_8__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SENSOR_8__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SENSOR_8__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SENSOR_8__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
SENSOR_8__0__HSIOM_MASK EQU 0x0000000F
SENSOR_8__0__HSIOM_SHIFT EQU 0
SENSOR_8__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_8__0__INTR EQU CYREG_GPIO_PRT2_INTR
SENSOR_8__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_8__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SENSOR_8__0__MASK EQU 0x01
SENSOR_8__0__OUT_SEL EQU CYREG_UDB_PA2_CFG10
SENSOR_8__0__OUT_SEL_SHIFT EQU 0
SENSOR_8__0__OUT_SEL_VAL EQU 1
SENSOR_8__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
SENSOR_8__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
SENSOR_8__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
SENSOR_8__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
SENSOR_8__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
SENSOR_8__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
SENSOR_8__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
SENSOR_8__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
SENSOR_8__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
SENSOR_8__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
SENSOR_8__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
SENSOR_8__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
SENSOR_8__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
SENSOR_8__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
SENSOR_8__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
SENSOR_8__0__PC EQU CYREG_GPIO_PRT2_PC
SENSOR_8__0__PC2 EQU CYREG_GPIO_PRT2_PC2
SENSOR_8__0__PORT EQU 2
SENSOR_8__0__PS EQU CYREG_GPIO_PRT2_PS
SENSOR_8__0__SHIFT EQU 0
SENSOR_8__DR EQU CYREG_GPIO_PRT2_DR
SENSOR_8__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SENSOR_8__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SENSOR_8__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SENSOR_8__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_8__INTR EQU CYREG_GPIO_PRT2_INTR
SENSOR_8__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_8__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SENSOR_8__MASK EQU 0x01
SENSOR_8__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
SENSOR_8__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
SENSOR_8__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
SENSOR_8__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
SENSOR_8__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
SENSOR_8__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
SENSOR_8__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
SENSOR_8__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
SENSOR_8__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
SENSOR_8__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
SENSOR_8__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
SENSOR_8__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
SENSOR_8__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
SENSOR_8__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
SENSOR_8__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
SENSOR_8__PC EQU CYREG_GPIO_PRT2_PC
SENSOR_8__PC2 EQU CYREG_GPIO_PRT2_PC2
SENSOR_8__PORT EQU 2
SENSOR_8__PS EQU CYREG_GPIO_PRT2_PS
SENSOR_8__SHIFT EQU 0

/* SENSOR_9 */
SENSOR_9__0__DR EQU CYREG_GPIO_PRT2_DR
SENSOR_9__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SENSOR_9__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SENSOR_9__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SENSOR_9__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
SENSOR_9__0__HSIOM_MASK EQU 0x000000F0
SENSOR_9__0__HSIOM_SHIFT EQU 4
SENSOR_9__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_9__0__INTR EQU CYREG_GPIO_PRT2_INTR
SENSOR_9__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_9__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SENSOR_9__0__MASK EQU 0x02
SENSOR_9__0__OUT_SEL EQU CYREG_UDB_PA2_CFG10
SENSOR_9__0__OUT_SEL_SHIFT EQU 2
SENSOR_9__0__OUT_SEL_VAL EQU 1
SENSOR_9__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
SENSOR_9__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
SENSOR_9__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
SENSOR_9__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
SENSOR_9__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
SENSOR_9__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
SENSOR_9__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
SENSOR_9__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
SENSOR_9__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
SENSOR_9__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
SENSOR_9__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
SENSOR_9__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
SENSOR_9__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
SENSOR_9__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
SENSOR_9__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
SENSOR_9__0__PC EQU CYREG_GPIO_PRT2_PC
SENSOR_9__0__PC2 EQU CYREG_GPIO_PRT2_PC2
SENSOR_9__0__PORT EQU 2
SENSOR_9__0__PS EQU CYREG_GPIO_PRT2_PS
SENSOR_9__0__SHIFT EQU 1
SENSOR_9__DR EQU CYREG_GPIO_PRT2_DR
SENSOR_9__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SENSOR_9__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SENSOR_9__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SENSOR_9__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_9__INTR EQU CYREG_GPIO_PRT2_INTR
SENSOR_9__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SENSOR_9__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SENSOR_9__MASK EQU 0x02
SENSOR_9__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
SENSOR_9__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
SENSOR_9__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
SENSOR_9__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
SENSOR_9__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
SENSOR_9__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
SENSOR_9__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
SENSOR_9__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
SENSOR_9__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
SENSOR_9__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
SENSOR_9__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
SENSOR_9__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
SENSOR_9__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
SENSOR_9__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
SENSOR_9__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
SENSOR_9__PC EQU CYREG_GPIO_PRT2_PC
SENSOR_9__PC2 EQU CYREG_GPIO_PRT2_PC2
SENSOR_9__PORT EQU 2
SENSOR_9__PS EQU CYREG_GPIO_PRT2_PS
SENSOR_9__SHIFT EQU 1

/* SW */
SW__0__DR EQU CYREG_GPIO_PRT2_DR
SW__0__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SW__0__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SW__0__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SW__0__HSIOM EQU CYREG_HSIOM_PORT_SEL2
SW__0__HSIOM_MASK EQU 0xF0000000
SW__0__HSIOM_SHIFT EQU 28
SW__0__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SW__0__INTR EQU CYREG_GPIO_PRT2_INTR
SW__0__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SW__0__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SW__0__MASK EQU 0x80
SW__0__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
SW__0__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
SW__0__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
SW__0__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
SW__0__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
SW__0__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
SW__0__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
SW__0__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
SW__0__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
SW__0__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
SW__0__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
SW__0__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
SW__0__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
SW__0__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
SW__0__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
SW__0__PC EQU CYREG_GPIO_PRT2_PC
SW__0__PC2 EQU CYREG_GPIO_PRT2_PC2
SW__0__PORT EQU 2
SW__0__PS EQU CYREG_GPIO_PRT2_PS
SW__0__SHIFT EQU 7
SW__DR EQU CYREG_GPIO_PRT2_DR
SW__DR_CLR EQU CYREG_GPIO_PRT2_DR_CLR
SW__DR_INV EQU CYREG_GPIO_PRT2_DR_INV
SW__DR_SET EQU CYREG_GPIO_PRT2_DR_SET
SW__INTCFG EQU CYREG_GPIO_PRT2_INTR_CFG
SW__INTR EQU CYREG_GPIO_PRT2_INTR
SW__INTR_CFG EQU CYREG_GPIO_PRT2_INTR_CFG
SW__INTSTAT EQU CYREG_GPIO_PRT2_INTR
SW__MASK EQU 0x80
SW__PA__CFG0 EQU CYREG_UDB_PA2_CFG0
SW__PA__CFG1 EQU CYREG_UDB_PA2_CFG1
SW__PA__CFG10 EQU CYREG_UDB_PA2_CFG10
SW__PA__CFG11 EQU CYREG_UDB_PA2_CFG11
SW__PA__CFG12 EQU CYREG_UDB_PA2_CFG12
SW__PA__CFG13 EQU CYREG_UDB_PA2_CFG13
SW__PA__CFG14 EQU CYREG_UDB_PA2_CFG14
SW__PA__CFG2 EQU CYREG_UDB_PA2_CFG2
SW__PA__CFG3 EQU CYREG_UDB_PA2_CFG3
SW__PA__CFG4 EQU CYREG_UDB_PA2_CFG4
SW__PA__CFG5 EQU CYREG_UDB_PA2_CFG5
SW__PA__CFG6 EQU CYREG_UDB_PA2_CFG6
SW__PA__CFG7 EQU CYREG_UDB_PA2_CFG7
SW__PA__CFG8 EQU CYREG_UDB_PA2_CFG8
SW__PA__CFG9 EQU CYREG_UDB_PA2_CFG9
SW__PC EQU CYREG_GPIO_PRT2_PC
SW__PC2 EQU CYREG_GPIO_PRT2_PC2
SW__PORT EQU 2
SW__PS EQU CYREG_GPIO_PRT2_PS
SW__SHIFT EQU 7

/* SwClk */
SwClk__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL11
SwClk__DIV_ID EQU 0x00000042
SwClk__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL2
SwClk__PA_DIV_ID EQU 0x000000FF

/* TC_ISR */
TC_ISR__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
TC_ISR__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
TC_ISR__INTC_MASK EQU 0x100000
TC_ISR__INTC_NUMBER EQU 20
TC_ISR__INTC_PRIOR_MASK EQU 0xC0
TC_ISR__INTC_PRIOR_NUM EQU 3
TC_ISR__INTC_PRIOR_REG EQU CYREG_CM0_IPR5
TC_ISR__INTC_SET_EN_REG EQU CYREG_CM0_ISER
TC_ISR__INTC_SET_PD_REG EQU CYREG_CM0_ISPR
TC_ISR_1__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
TC_ISR_1__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
TC_ISR_1__INTC_MASK EQU 0x20000
TC_ISR_1__INTC_NUMBER EQU 17
TC_ISR_1__INTC_PRIOR_MASK EQU 0xC000
TC_ISR_1__INTC_PRIOR_NUM EQU 3
TC_ISR_1__INTC_PRIOR_REG EQU CYREG_CM0_IPR4
TC_ISR_1__INTC_SET_EN_REG EQU CYREG_CM0_ISER
TC_ISR_1__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* Timer_1_TimerUDB */
Timer_1_TimerUDB_rstSts_stsreg__0__MASK EQU 0x01
Timer_1_TimerUDB_rstSts_stsreg__0__POS EQU 0
Timer_1_TimerUDB_rstSts_stsreg__2__MASK EQU 0x04
Timer_1_TimerUDB_rstSts_stsreg__2__POS EQU 2
Timer_1_TimerUDB_rstSts_stsreg__3__MASK EQU 0x08
Timer_1_TimerUDB_rstSts_stsreg__3__POS EQU 3
Timer_1_TimerUDB_rstSts_stsreg__MASK EQU 0x0D
Timer_1_TimerUDB_rstSts_stsreg__MASK_REG EQU CYREG_UDB_W8_MSK3
Timer_1_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL3
Timer_1_TimerUDB_rstSts_stsreg__STATUS_REG EQU CYREG_UDB_W8_ST3
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_UDB_W16_ACTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG EQU CYREG_UDB_W16_CTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG EQU CYREG_UDB_W16_CTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG EQU CYREG_UDB_W16_CTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG EQU CYREG_UDB_W16_CTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_MASK_REG EQU CYREG_UDB_W16_MSK0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG EQU CYREG_UDB_W16_MSK0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG EQU CYREG_UDB_W16_MSK0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG EQU CYREG_UDB_W16_MSK0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_CONTROL_AUX_CTL_REG EQU CYREG_UDB_W32_ACTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_CONTROL_REG EQU CYREG_UDB_W32_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_COUNT_REG EQU CYREG_UDB_W32_CTL
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_PERIOD_REG EQU CYREG_UDB_W32_MSK
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__MASK EQU 0x80
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__POS EQU 7
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG EQU CYREG_UDB_W8_CTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_ST_REG EQU CYREG_UDB_CAT16_CTL_ST0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_REG EQU CYREG_UDB_W8_CTL0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_ST_REG EQU CYREG_UDB_CAT16_CTL_ST0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK EQU 0x80
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK0
Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PERIOD_REG EQU CYREG_UDB_W8_MSK0
Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_A0_REG EQU CYREG_UDB_W16_A00
Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_A1_REG EQU CYREG_UDB_W16_A10
Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_D0_REG EQU CYREG_UDB_W16_D00
Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_D1_REG EQU CYREG_UDB_W16_D10
Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_UDB_W16_ACTL0
Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_F0_REG EQU CYREG_UDB_W16_F00
Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_F1_REG EQU CYREG_UDB_W16_F10
Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_A0_REG EQU CYREG_UDB_W32_A0
Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_A1_REG EQU CYREG_UDB_W32_A1
Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_D0_REG EQU CYREG_UDB_W32_D0
Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_D1_REG EQU CYREG_UDB_W32_D1
Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_DP_AUX_CTL_REG EQU CYREG_UDB_W32_ACTL
Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_F0_REG EQU CYREG_UDB_W32_F0
Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_F1_REG EQU CYREG_UDB_W32_F1
Timer_1_TimerUDB_sT32_timerdp_u0__A0_A1_REG EQU CYREG_UDB_CAT16_A0
Timer_1_TimerUDB_sT32_timerdp_u0__A0_REG EQU CYREG_UDB_W8_A00
Timer_1_TimerUDB_sT32_timerdp_u0__A1_REG EQU CYREG_UDB_W8_A10
Timer_1_TimerUDB_sT32_timerdp_u0__D0_D1_REG EQU CYREG_UDB_CAT16_D0
Timer_1_TimerUDB_sT32_timerdp_u0__D0_REG EQU CYREG_UDB_W8_D00
Timer_1_TimerUDB_sT32_timerdp_u0__D1_REG EQU CYREG_UDB_W8_D10
Timer_1_TimerUDB_sT32_timerdp_u0__DP_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL0
Timer_1_TimerUDB_sT32_timerdp_u0__F0_F1_REG EQU CYREG_UDB_CAT16_F0
Timer_1_TimerUDB_sT32_timerdp_u0__F0_REG EQU CYREG_UDB_W8_F00
Timer_1_TimerUDB_sT32_timerdp_u0__F1_REG EQU CYREG_UDB_W8_F10
Timer_1_TimerUDB_sT32_timerdp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK0
Timer_1_TimerUDB_sT32_timerdp_u0__PER_DP_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK0
Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_A0_REG EQU CYREG_UDB_W16_A01
Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_A1_REG EQU CYREG_UDB_W16_A11
Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_D0_REG EQU CYREG_UDB_W16_D01
Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_D1_REG EQU CYREG_UDB_W16_D11
Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_DP_AUX_CTL_REG EQU CYREG_UDB_W16_ACTL1
Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_F0_REG EQU CYREG_UDB_W16_F01
Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_F1_REG EQU CYREG_UDB_W16_F11
Timer_1_TimerUDB_sT32_timerdp_u1__A0_A1_REG EQU CYREG_UDB_CAT16_A1
Timer_1_TimerUDB_sT32_timerdp_u1__A0_REG EQU CYREG_UDB_W8_A01
Timer_1_TimerUDB_sT32_timerdp_u1__A1_REG EQU CYREG_UDB_W8_A11
Timer_1_TimerUDB_sT32_timerdp_u1__D0_D1_REG EQU CYREG_UDB_CAT16_D1
Timer_1_TimerUDB_sT32_timerdp_u1__D0_REG EQU CYREG_UDB_W8_D01
Timer_1_TimerUDB_sT32_timerdp_u1__D1_REG EQU CYREG_UDB_W8_D11
Timer_1_TimerUDB_sT32_timerdp_u1__DP_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL1
Timer_1_TimerUDB_sT32_timerdp_u1__F0_F1_REG EQU CYREG_UDB_CAT16_F1
Timer_1_TimerUDB_sT32_timerdp_u1__F0_REG EQU CYREG_UDB_W8_F01
Timer_1_TimerUDB_sT32_timerdp_u1__F1_REG EQU CYREG_UDB_W8_F11
Timer_1_TimerUDB_sT32_timerdp_u1__MSK_DP_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK1
Timer_1_TimerUDB_sT32_timerdp_u1__PER_DP_AUX_CTL_REG EQU CYREG_UDB_CAT16_ACTL_MSK1
Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_A0_REG EQU CYREG_UDB_W16_A02
Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_A1_REG EQU CYREG_UDB_W16_A12
Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_D0_REG EQU CYREG_UDB_W16_D02
Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_D1_REG EQU CYREG_UDB_W16_D12
Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_DP_AUX_CTL_REG EQU CYREG_UDB_W16_ACTL2
Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_F0_REG EQU CYREG_UDB_W16_F02
Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_F1_REG EQU CYREG_UDB_W16_F12
Timer_1_TimerUDB_sT32_timerdp_u2__A0_A1_REG EQU CYREG_UDB_CAT16_A2
Timer_1_TimerUDB_sT32_timerdp_u2__A0_REG EQU CYREG_UDB_W8_A02
Timer_1_TimerUDB_sT32_timerdp_u2__A1_REG EQU CYREG_UDB_W8_A12
Timer_1_TimerUDB_sT32_timerdp_u2__D0_D1_REG EQU CYREG_UDB_CAT16_D2
Timer_1_TimerUDB_sT32_timerdp_u2__D0_REG EQU CYREG_UDB_W8_D02
Timer_1_TimerUDB_sT32_timerdp_u2__D1_REG EQU CYREG_UDB_W8_D12
Timer_1_TimerUDB_sT32_timerdp_u2__DP_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL2
Timer_1_TimerUDB_sT32_timerdp_u2__F0_F1_REG EQU CYREG_UDB_CAT16_F2
Timer_1_TimerUDB_sT32_timerdp_u2__F0_REG EQU CYREG_UDB_W8_F02
Timer_1_TimerUDB_sT32_timerdp_u2__F1_REG EQU CYREG_UDB_W8_F12
Timer_1_TimerUDB_sT32_timerdp_u3__A0_A1_REG EQU CYREG_UDB_CAT16_A3
Timer_1_TimerUDB_sT32_timerdp_u3__A0_REG EQU CYREG_UDB_W8_A03
Timer_1_TimerUDB_sT32_timerdp_u3__A1_REG EQU CYREG_UDB_W8_A13
Timer_1_TimerUDB_sT32_timerdp_u3__D0_D1_REG EQU CYREG_UDB_CAT16_D3
Timer_1_TimerUDB_sT32_timerdp_u3__D0_REG EQU CYREG_UDB_W8_D03
Timer_1_TimerUDB_sT32_timerdp_u3__D1_REG EQU CYREG_UDB_W8_D13
Timer_1_TimerUDB_sT32_timerdp_u3__DP_AUX_CTL_REG EQU CYREG_UDB_W8_ACTL3
Timer_1_TimerUDB_sT32_timerdp_u3__F0_F1_REG EQU CYREG_UDB_CAT16_F3
Timer_1_TimerUDB_sT32_timerdp_u3__F0_REG EQU CYREG_UDB_W8_F03
Timer_1_TimerUDB_sT32_timerdp_u3__F1_REG EQU CYREG_UDB_W8_F13

/* UART */
UART_rx__0__DR EQU CYREG_GPIO_PRT1_DR
UART_rx__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_rx__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_rx__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_rx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
UART_rx__0__HSIOM_GPIO EQU 0
UART_rx__0__HSIOM_I2C EQU 14
UART_rx__0__HSIOM_I2C_SDA EQU 14
UART_rx__0__HSIOM_MASK EQU 0x000F0000
UART_rx__0__HSIOM_SHIFT EQU 16
UART_rx__0__HSIOM_SPI EQU 15
UART_rx__0__HSIOM_SPI_MOSI EQU 15
UART_rx__0__HSIOM_UART EQU 9
UART_rx__0__HSIOM_UART_RX EQU 9
UART_rx__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__0__INTR EQU CYREG_GPIO_PRT1_INTR
UART_rx__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_rx__0__MASK EQU 0x10
UART_rx__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_rx__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_rx__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_rx__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_rx__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_rx__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_rx__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_rx__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_rx__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_rx__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_rx__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_rx__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_rx__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_rx__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_rx__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_rx__0__PC EQU CYREG_GPIO_PRT1_PC
UART_rx__0__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_rx__0__PORT EQU 1
UART_rx__0__PS EQU CYREG_GPIO_PRT1_PS
UART_rx__0__SHIFT EQU 4
UART_rx__DR EQU CYREG_GPIO_PRT1_DR
UART_rx__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_rx__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_rx__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_rx__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__INTR EQU CYREG_GPIO_PRT1_INTR
UART_rx__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_rx__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_rx__MASK EQU 0x10
UART_rx__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_rx__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_rx__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_rx__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_rx__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_rx__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_rx__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_rx__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_rx__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_rx__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_rx__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_rx__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_rx__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_rx__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_rx__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_rx__PC EQU CYREG_GPIO_PRT1_PC
UART_rx__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_rx__PORT EQU 1
UART_rx__PS EQU CYREG_GPIO_PRT1_PS
UART_rx__SHIFT EQU 4
UART_SCB__CTRL EQU CYREG_SCB0_CTRL
UART_SCB__EZ_DATA0 EQU CYREG_SCB0_EZ_DATA0
UART_SCB__EZ_DATA1 EQU CYREG_SCB0_EZ_DATA1
UART_SCB__EZ_DATA10 EQU CYREG_SCB0_EZ_DATA10
UART_SCB__EZ_DATA11 EQU CYREG_SCB0_EZ_DATA11
UART_SCB__EZ_DATA12 EQU CYREG_SCB0_EZ_DATA12
UART_SCB__EZ_DATA13 EQU CYREG_SCB0_EZ_DATA13
UART_SCB__EZ_DATA14 EQU CYREG_SCB0_EZ_DATA14
UART_SCB__EZ_DATA15 EQU CYREG_SCB0_EZ_DATA15
UART_SCB__EZ_DATA16 EQU CYREG_SCB0_EZ_DATA16
UART_SCB__EZ_DATA17 EQU CYREG_SCB0_EZ_DATA17
UART_SCB__EZ_DATA18 EQU CYREG_SCB0_EZ_DATA18
UART_SCB__EZ_DATA19 EQU CYREG_SCB0_EZ_DATA19
UART_SCB__EZ_DATA2 EQU CYREG_SCB0_EZ_DATA2
UART_SCB__EZ_DATA20 EQU CYREG_SCB0_EZ_DATA20
UART_SCB__EZ_DATA21 EQU CYREG_SCB0_EZ_DATA21
UART_SCB__EZ_DATA22 EQU CYREG_SCB0_EZ_DATA22
UART_SCB__EZ_DATA23 EQU CYREG_SCB0_EZ_DATA23
UART_SCB__EZ_DATA24 EQU CYREG_SCB0_EZ_DATA24
UART_SCB__EZ_DATA25 EQU CYREG_SCB0_EZ_DATA25
UART_SCB__EZ_DATA26 EQU CYREG_SCB0_EZ_DATA26
UART_SCB__EZ_DATA27 EQU CYREG_SCB0_EZ_DATA27
UART_SCB__EZ_DATA28 EQU CYREG_SCB0_EZ_DATA28
UART_SCB__EZ_DATA29 EQU CYREG_SCB0_EZ_DATA29
UART_SCB__EZ_DATA3 EQU CYREG_SCB0_EZ_DATA3
UART_SCB__EZ_DATA30 EQU CYREG_SCB0_EZ_DATA30
UART_SCB__EZ_DATA31 EQU CYREG_SCB0_EZ_DATA31
UART_SCB__EZ_DATA4 EQU CYREG_SCB0_EZ_DATA4
UART_SCB__EZ_DATA5 EQU CYREG_SCB0_EZ_DATA5
UART_SCB__EZ_DATA6 EQU CYREG_SCB0_EZ_DATA6
UART_SCB__EZ_DATA7 EQU CYREG_SCB0_EZ_DATA7
UART_SCB__EZ_DATA8 EQU CYREG_SCB0_EZ_DATA8
UART_SCB__EZ_DATA9 EQU CYREG_SCB0_EZ_DATA9
UART_SCB__I2C_CFG EQU CYREG_SCB0_I2C_CFG
UART_SCB__I2C_CTRL EQU CYREG_SCB0_I2C_CTRL
UART_SCB__I2C_M_CMD EQU CYREG_SCB0_I2C_M_CMD
UART_SCB__I2C_S_CMD EQU CYREG_SCB0_I2C_S_CMD
UART_SCB__I2C_STATUS EQU CYREG_SCB0_I2C_STATUS
UART_SCB__INTR_CAUSE EQU CYREG_SCB0_INTR_CAUSE
UART_SCB__INTR_I2C_EC EQU CYREG_SCB0_INTR_I2C_EC
UART_SCB__INTR_I2C_EC_MASK EQU CYREG_SCB0_INTR_I2C_EC_MASK
UART_SCB__INTR_I2C_EC_MASKED EQU CYREG_SCB0_INTR_I2C_EC_MASKED
UART_SCB__INTR_M EQU CYREG_SCB0_INTR_M
UART_SCB__INTR_M_MASK EQU CYREG_SCB0_INTR_M_MASK
UART_SCB__INTR_M_MASKED EQU CYREG_SCB0_INTR_M_MASKED
UART_SCB__INTR_M_SET EQU CYREG_SCB0_INTR_M_SET
UART_SCB__INTR_RX EQU CYREG_SCB0_INTR_RX
UART_SCB__INTR_RX_MASK EQU CYREG_SCB0_INTR_RX_MASK
UART_SCB__INTR_RX_MASKED EQU CYREG_SCB0_INTR_RX_MASKED
UART_SCB__INTR_RX_SET EQU CYREG_SCB0_INTR_RX_SET
UART_SCB__INTR_S EQU CYREG_SCB0_INTR_S
UART_SCB__INTR_S_MASK EQU CYREG_SCB0_INTR_S_MASK
UART_SCB__INTR_S_MASKED EQU CYREG_SCB0_INTR_S_MASKED
UART_SCB__INTR_S_SET EQU CYREG_SCB0_INTR_S_SET
UART_SCB__INTR_SPI_EC EQU CYREG_SCB0_INTR_SPI_EC
UART_SCB__INTR_SPI_EC_MASK EQU CYREG_SCB0_INTR_SPI_EC_MASK
UART_SCB__INTR_SPI_EC_MASKED EQU CYREG_SCB0_INTR_SPI_EC_MASKED
UART_SCB__INTR_TX EQU CYREG_SCB0_INTR_TX
UART_SCB__INTR_TX_MASK EQU CYREG_SCB0_INTR_TX_MASK
UART_SCB__INTR_TX_MASKED EQU CYREG_SCB0_INTR_TX_MASKED
UART_SCB__INTR_TX_SET EQU CYREG_SCB0_INTR_TX_SET
UART_SCB__RX_CTRL EQU CYREG_SCB0_RX_CTRL
UART_SCB__RX_FIFO_CTRL EQU CYREG_SCB0_RX_FIFO_CTRL
UART_SCB__RX_FIFO_RD EQU CYREG_SCB0_RX_FIFO_RD
UART_SCB__RX_FIFO_RD_SILENT EQU CYREG_SCB0_RX_FIFO_RD_SILENT
UART_SCB__RX_FIFO_STATUS EQU CYREG_SCB0_RX_FIFO_STATUS
UART_SCB__RX_MATCH EQU CYREG_SCB0_RX_MATCH
UART_SCB__SPI_CTRL EQU CYREG_SCB0_SPI_CTRL
UART_SCB__SPI_STATUS EQU CYREG_SCB0_SPI_STATUS
UART_SCB__SS0_POSISTION EQU 0
UART_SCB__SS1_POSISTION EQU 1
UART_SCB__SS2_POSISTION EQU 2
UART_SCB__SS3_POSISTION EQU 3
UART_SCB__STATUS EQU CYREG_SCB0_STATUS
UART_SCB__TX_CTRL EQU CYREG_SCB0_TX_CTRL
UART_SCB__TX_FIFO_CTRL EQU CYREG_SCB0_TX_FIFO_CTRL
UART_SCB__TX_FIFO_STATUS EQU CYREG_SCB0_TX_FIFO_STATUS
UART_SCB__TX_FIFO_WR EQU CYREG_SCB0_TX_FIFO_WR
UART_SCB__UART_CTRL EQU CYREG_SCB0_UART_CTRL
UART_SCB__UART_FLOW_CTRL EQU CYREG_SCB0_UART_FLOW_CTRL
UART_SCB__UART_RX_CTRL EQU CYREG_SCB0_UART_RX_CTRL
UART_SCB__UART_RX_STATUS EQU CYREG_SCB0_UART_RX_STATUS
UART_SCB__UART_TX_CTRL EQU CYREG_SCB0_UART_TX_CTRL
UART_SCBCLK__CTRL_REGISTER EQU CYREG_PERI_PCLK_CTL1
UART_SCBCLK__DIV_ID EQU 0x00000040
UART_SCBCLK__DIV_REGISTER EQU CYREG_PERI_DIV_16_CTL0
UART_SCBCLK__PA_DIV_ID EQU 0x000000FF
UART_tx__0__DR EQU CYREG_GPIO_PRT1_DR
UART_tx__0__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_tx__0__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_tx__0__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_tx__0__HSIOM EQU CYREG_HSIOM_PORT_SEL1
UART_tx__0__HSIOM_GPIO EQU 0
UART_tx__0__HSIOM_I2C EQU 14
UART_tx__0__HSIOM_I2C_SCL EQU 14
UART_tx__0__HSIOM_MASK EQU 0x00F00000
UART_tx__0__HSIOM_SHIFT EQU 20
UART_tx__0__HSIOM_SPI EQU 15
UART_tx__0__HSIOM_SPI_MISO EQU 15
UART_tx__0__HSIOM_UART EQU 9
UART_tx__0__HSIOM_UART_TX EQU 9
UART_tx__0__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__0__INTR EQU CYREG_GPIO_PRT1_INTR
UART_tx__0__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__0__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_tx__0__MASK EQU 0x20
UART_tx__0__OUT_SEL EQU CYREG_UDB_PA1_CFG10
UART_tx__0__OUT_SEL_SHIFT EQU 10
UART_tx__0__OUT_SEL_VAL EQU -1
UART_tx__0__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_tx__0__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_tx__0__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_tx__0__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_tx__0__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_tx__0__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_tx__0__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_tx__0__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_tx__0__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_tx__0__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_tx__0__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_tx__0__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_tx__0__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_tx__0__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_tx__0__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_tx__0__PC EQU CYREG_GPIO_PRT1_PC
UART_tx__0__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_tx__0__PORT EQU 1
UART_tx__0__PS EQU CYREG_GPIO_PRT1_PS
UART_tx__0__SHIFT EQU 5
UART_tx__DR EQU CYREG_GPIO_PRT1_DR
UART_tx__DR_CLR EQU CYREG_GPIO_PRT1_DR_CLR
UART_tx__DR_INV EQU CYREG_GPIO_PRT1_DR_INV
UART_tx__DR_SET EQU CYREG_GPIO_PRT1_DR_SET
UART_tx__INTCFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__INTR EQU CYREG_GPIO_PRT1_INTR
UART_tx__INTR_CFG EQU CYREG_GPIO_PRT1_INTR_CFG
UART_tx__INTSTAT EQU CYREG_GPIO_PRT1_INTR
UART_tx__MASK EQU 0x20
UART_tx__PA__CFG0 EQU CYREG_UDB_PA1_CFG0
UART_tx__PA__CFG1 EQU CYREG_UDB_PA1_CFG1
UART_tx__PA__CFG10 EQU CYREG_UDB_PA1_CFG10
UART_tx__PA__CFG11 EQU CYREG_UDB_PA1_CFG11
UART_tx__PA__CFG12 EQU CYREG_UDB_PA1_CFG12
UART_tx__PA__CFG13 EQU CYREG_UDB_PA1_CFG13
UART_tx__PA__CFG14 EQU CYREG_UDB_PA1_CFG14
UART_tx__PA__CFG2 EQU CYREG_UDB_PA1_CFG2
UART_tx__PA__CFG3 EQU CYREG_UDB_PA1_CFG3
UART_tx__PA__CFG4 EQU CYREG_UDB_PA1_CFG4
UART_tx__PA__CFG5 EQU CYREG_UDB_PA1_CFG5
UART_tx__PA__CFG6 EQU CYREG_UDB_PA1_CFG6
UART_tx__PA__CFG7 EQU CYREG_UDB_PA1_CFG7
UART_tx__PA__CFG8 EQU CYREG_UDB_PA1_CFG8
UART_tx__PA__CFG9 EQU CYREG_UDB_PA1_CFG9
UART_tx__PC EQU CYREG_GPIO_PRT1_PC
UART_tx__PC2 EQU CYREG_GPIO_PRT1_PC2
UART_tx__PORT EQU 1
UART_tx__PS EQU CYREG_GPIO_PRT1_PS
UART_tx__SHIFT EQU 5

/* isr_1 */
isr_1__INTC_CLR_EN_REG EQU CYREG_CM0_ICER
isr_1__INTC_CLR_PD_REG EQU CYREG_CM0_ICPR
isr_1__INTC_MASK EQU 0x04
isr_1__INTC_NUMBER EQU 2
isr_1__INTC_PRIOR_MASK EQU 0xC00000
isr_1__INTC_PRIOR_NUM EQU 3
isr_1__INTC_PRIOR_REG EQU CYREG_CM0_IPR0
isr_1__INTC_SET_EN_REG EQU CYREG_CM0_ISER
isr_1__INTC_SET_PD_REG EQU CYREG_CM0_ISPR

/* Miscellaneous */
CYDEV_BCLK__HFCLK__HZ EQU 24000000
CYDEV_BCLK__HFCLK__KHZ EQU 24000
CYDEV_BCLK__HFCLK__MHZ EQU 24
CYDEV_BCLK__SYSCLK__HZ EQU 24000000
CYDEV_BCLK__SYSCLK__KHZ EQU 24000
CYDEV_BCLK__SYSCLK__MHZ EQU 24
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PSOC4A EQU 16
CYDEV_CHIP_DIE_PSOC5LP EQU 2
CYDEV_CHIP_DIE_PSOC5TM EQU 3
CYDEV_CHIP_DIE_TMA4 EQU 4
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_FM0P EQU 5
CYDEV_CHIP_FAMILY_FM3 EQU 6
CYDEV_CHIP_FAMILY_FM4 EQU 7
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_PSOC6 EQU 4
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC4
CYDEV_CHIP_JTAG_ID EQU 0x0E34119E
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 16
CYDEV_CHIP_MEMBER_4D EQU 12
CYDEV_CHIP_MEMBER_4E EQU 6
CYDEV_CHIP_MEMBER_4F EQU 17
CYDEV_CHIP_MEMBER_4G EQU 4
CYDEV_CHIP_MEMBER_4H EQU 15
CYDEV_CHIP_MEMBER_4I EQU 21
CYDEV_CHIP_MEMBER_4J EQU 13
CYDEV_CHIP_MEMBER_4K EQU 14
CYDEV_CHIP_MEMBER_4L EQU 20
CYDEV_CHIP_MEMBER_4M EQU 19
CYDEV_CHIP_MEMBER_4N EQU 9
CYDEV_CHIP_MEMBER_4O EQU 7
CYDEV_CHIP_MEMBER_4P EQU 18
CYDEV_CHIP_MEMBER_4Q EQU 11
CYDEV_CHIP_MEMBER_4R EQU 8
CYDEV_CHIP_MEMBER_4S EQU 10
CYDEV_CHIP_MEMBER_4U EQU 5
CYDEV_CHIP_MEMBER_5A EQU 3
CYDEV_CHIP_MEMBER_5B EQU 2
CYDEV_CHIP_MEMBER_6A EQU 22
CYDEV_CHIP_MEMBER_FM3 EQU 26
CYDEV_CHIP_MEMBER_FM4 EQU 27
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24
CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_4F
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1
CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0
CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_4F_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_READ_ACCELERATOR EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_Disallowed
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_PROTECT_KILL EQU 4
CYDEV_DEBUG_PROTECT_OPEN EQU 1
CYDEV_DEBUG_PROTECT EQU CYDEV_DEBUG_PROTECT_OPEN
CYDEV_DEBUG_PROTECT_PROTECTED EQU 2
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DFT_SELECT_CLK0 EQU 10
CYDEV_DFT_SELECT_CLK1 EQU 11
CYDEV_HEAP_SIZE EQU 0x200
CYDEV_IMO_TRIMMED_BY_USB EQU 0
CYDEV_IMO_TRIMMED_BY_WCO EQU 0
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 1
CYDEV_VDDA_MV EQU 3300
CYDEV_VDDD_MV EQU 3300
CYDEV_VDDR_MV EQU 3300
CYDEV_WDT_GENERATE_ISR EQU 1
CYIPBLOCK_m0s8bless_VERSION EQU 1
CYIPBLOCK_m0s8cpussv2_VERSION EQU 1
CYIPBLOCK_m0s8csd_VERSION EQU 1
CYIPBLOCK_m0s8ioss_VERSION EQU 1
CYIPBLOCK_m0s8lcd_VERSION EQU 2
CYIPBLOCK_m0s8lpcomp_VERSION EQU 2
CYIPBLOCK_m0s8peri_VERSION EQU 1
CYIPBLOCK_m0s8scb_VERSION EQU 2
CYIPBLOCK_m0s8srssv2_VERSION EQU 1
CYIPBLOCK_m0s8tcpwm_VERSION EQU 2
CYIPBLOCK_m0s8udbif_VERSION EQU 1
CYIPBLOCK_s8pass4al_VERSION EQU 1
CYDEV_BOOTLOADER_ENABLE EQU 0

#endif /* INCLUDED_CYFITTERIAR_INC */
