/*******************************************************************************
* File Name: cyfittergnu.inc
* 
* PSoC Creator  4.1 Update 1
*
* Description:
* 
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

.ifndef INCLUDED_CYFITTERGNU_INC
.set INCLUDED_CYFITTERGNU_INC, 1
.include "cydevicegnu_trm.inc"

/* ADC */
.set ADC_cy_psoc4_sar__CLOCK_DIV_ID, 0x00000041
.set ADC_cy_psoc4_sar__SAR_ANA_TRIM, CYREG_SAR_ANA_TRIM
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00, CYREG_SAR_CHAN_CONFIG0
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01, CYREG_SAR_CHAN_CONFIG1
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02, CYREG_SAR_CHAN_CONFIG2
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03, CYREG_SAR_CHAN_CONFIG3
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04, CYREG_SAR_CHAN_CONFIG4
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05, CYREG_SAR_CHAN_CONFIG5
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06, CYREG_SAR_CHAN_CONFIG6
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07, CYREG_SAR_CHAN_CONFIG7
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG08, CYREG_SAR_CHAN_CONFIG8
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG09, CYREG_SAR_CHAN_CONFIG9
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG10, CYREG_SAR_CHAN_CONFIG10
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG11, CYREG_SAR_CHAN_CONFIG11
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG12, CYREG_SAR_CHAN_CONFIG12
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG13, CYREG_SAR_CHAN_CONFIG13
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG14, CYREG_SAR_CHAN_CONFIG14
.set ADC_cy_psoc4_sar__SAR_CHAN_CONFIG15, CYREG_SAR_CHAN_CONFIG15
.set ADC_cy_psoc4_sar__SAR_CHAN_EN, CYREG_SAR_CHAN_EN
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID, CYREG_SAR_CHAN_RESULT_VALID
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT00, CYREG_SAR_CHAN_RESULT0
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT01, CYREG_SAR_CHAN_RESULT1
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT02, CYREG_SAR_CHAN_RESULT2
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT03, CYREG_SAR_CHAN_RESULT3
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT04, CYREG_SAR_CHAN_RESULT4
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT05, CYREG_SAR_CHAN_RESULT5
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT06, CYREG_SAR_CHAN_RESULT6
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT07, CYREG_SAR_CHAN_RESULT7
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT08, CYREG_SAR_CHAN_RESULT8
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT09, CYREG_SAR_CHAN_RESULT9
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT10, CYREG_SAR_CHAN_RESULT10
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT11, CYREG_SAR_CHAN_RESULT11
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT12, CYREG_SAR_CHAN_RESULT12
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT13, CYREG_SAR_CHAN_RESULT13
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT14, CYREG_SAR_CHAN_RESULT14
.set ADC_cy_psoc4_sar__SAR_CHAN_RESULT15, CYREG_SAR_CHAN_RESULT15
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID, CYREG_SAR_CHAN_WORK_VALID
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK00, CYREG_SAR_CHAN_WORK0
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK01, CYREG_SAR_CHAN_WORK1
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK02, CYREG_SAR_CHAN_WORK2
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK03, CYREG_SAR_CHAN_WORK3
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK04, CYREG_SAR_CHAN_WORK4
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK05, CYREG_SAR_CHAN_WORK5
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK06, CYREG_SAR_CHAN_WORK6
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK07, CYREG_SAR_CHAN_WORK7
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK08, CYREG_SAR_CHAN_WORK8
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK09, CYREG_SAR_CHAN_WORK9
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK10, CYREG_SAR_CHAN_WORK10
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK11, CYREG_SAR_CHAN_WORK11
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK12, CYREG_SAR_CHAN_WORK12
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK13, CYREG_SAR_CHAN_WORK13
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK14, CYREG_SAR_CHAN_WORK14
.set ADC_cy_psoc4_sar__SAR_CHAN_WORK15, CYREG_SAR_CHAN_WORK15
.set ADC_cy_psoc4_sar__SAR_CTRL, CYREG_SAR_CTRL
.set ADC_cy_psoc4_sar__SAR_DFT_CTRL, CYREG_SAR_DFT_CTRL
.set ADC_cy_psoc4_sar__SAR_INTR, CYREG_SAR_INTR
.set ADC_cy_psoc4_sar__SAR_INTR_CAUSE, CYREG_SAR_INTR_CAUSE
.set ADC_cy_psoc4_sar__SAR_INTR_MASK, CYREG_SAR_INTR_MASK
.set ADC_cy_psoc4_sar__SAR_INTR_MASKED, CYREG_SAR_INTR_MASKED
.set ADC_cy_psoc4_sar__SAR_INTR_SET, CYREG_SAR_INTR_SET
.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL, CYREG_SAR_MUX_SWITCH_HW_CTRL
.set ADC_cy_psoc4_sar__SAR_MUX_SWITCH0, CYREG_SAR_MUX_SWITCH0
.set ADC_cy_psoc4_sar__SAR_NUMBER, 0
.set ADC_cy_psoc4_sar__SAR_PUMP_CTRL, CYREG_SAR_PUMP_CTRL
.set ADC_cy_psoc4_sar__SAR_RANGE_COND, CYREG_SAR_RANGE_COND
.set ADC_cy_psoc4_sar__SAR_RANGE_INTR, CYREG_SAR_RANGE_INTR
.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK, CYREG_SAR_RANGE_INTR_MASK
.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED, CYREG_SAR_RANGE_INTR_MASKED
.set ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET, CYREG_SAR_RANGE_INTR_SET
.set ADC_cy_psoc4_sar__SAR_RANGE_THRES, CYREG_SAR_RANGE_THRES
.set ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL, CYREG_SAR_SAMPLE_CTRL
.set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01, CYREG_SAR_SAMPLE_TIME01
.set ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23, CYREG_SAR_SAMPLE_TIME23
.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR, CYREG_SAR_SATURATE_INTR
.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK, CYREG_SAR_SATURATE_INTR_MASK
.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED, CYREG_SAR_SATURATE_INTR_MASKED
.set ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET, CYREG_SAR_SATURATE_INTR_SET
.set ADC_cy_psoc4_sar__SAR_START_CTRL, CYREG_SAR_START_CTRL
.set ADC_cy_psoc4_sar__SAR_STATUS, CYREG_SAR_STATUS
.set ADC_cy_psoc4_sar__SAR_WOUNDING, CYREG_SAR_WOUNDING
.set ADC_intClock__CTRL_REGISTER, CYREG_PERI_PCLK_CTL6
.set ADC_intClock__DIV_ID, 0x00000041
.set ADC_intClock__DIV_REGISTER, CYREG_PERI_DIV_16_CTL1
.set ADC_intClock__PA_DIV_ID, 0x000000FF
.set ADC_IRQ__INTC_CLR_EN_REG, CYREG_CM0_ICER
.set ADC_IRQ__INTC_CLR_PD_REG, CYREG_CM0_ICPR
.set ADC_IRQ__INTC_MASK, 0x8000
.set ADC_IRQ__INTC_NUMBER, 15
.set ADC_IRQ__INTC_PRIOR_MASK, 0xC0000000
.set ADC_IRQ__INTC_PRIOR_NUM, 3
.set ADC_IRQ__INTC_PRIOR_REG, CYREG_CM0_IPR3
.set ADC_IRQ__INTC_SET_EN_REG, CYREG_CM0_ISER
.set ADC_IRQ__INTC_SET_PD_REG, CYREG_CM0_ISPR

/* FiltInt */
.set FiltInt__INTC_CLR_EN_REG, CYREG_CM0_ICER
.set FiltInt__INTC_CLR_PD_REG, CYREG_CM0_ICPR
.set FiltInt__INTC_MASK, 0x02
.set FiltInt__INTC_NUMBER, 1
.set FiltInt__INTC_PRIOR_MASK, 0xC000
.set FiltInt__INTC_PRIOR_NUM, 3
.set FiltInt__INTC_PRIOR_REG, CYREG_CM0_IPR0
.set FiltInt__INTC_SET_EN_REG, CYREG_CM0_ISER
.set FiltInt__INTC_SET_PD_REG, CYREG_CM0_ISPR

/* FiltReset */
.set FiltReset_Sync_ctrl_reg__0__MASK, 0x01
.set FiltReset_Sync_ctrl_reg__0__POS, 0
.set FiltReset_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_UDB_W16_ACTL1
.set FiltReset_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_UDB_W16_CTL1
.set FiltReset_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_UDB_W16_CTL1
.set FiltReset_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_UDB_W16_CTL1
.set FiltReset_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_UDB_W16_CTL1
.set FiltReset_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_UDB_W16_MSK1
.set FiltReset_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_UDB_W16_MSK1
.set FiltReset_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_UDB_W16_MSK1
.set FiltReset_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_UDB_W16_MSK1
.set FiltReset_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_UDB_W8_ACTL1
.set FiltReset_Sync_ctrl_reg__CONTROL_REG, CYREG_UDB_W8_CTL1
.set FiltReset_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_UDB_CAT16_CTL_ST1
.set FiltReset_Sync_ctrl_reg__COUNT_REG, CYREG_UDB_W8_CTL1
.set FiltReset_Sync_ctrl_reg__COUNT_ST_REG, CYREG_UDB_CAT16_CTL_ST1
.set FiltReset_Sync_ctrl_reg__MASK, 0x01
.set FiltReset_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK1
.set FiltReset_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK1
.set FiltReset_Sync_ctrl_reg__PERIOD_REG, CYREG_UDB_W8_MSK1

/* IDAC */
.set IDAC_cy_psoc4_idac__CONTROL, CYREG_CSD_CONFIG
.set IDAC_cy_psoc4_idac__CSD_IDAC, CYREG_CSD_IDAC
.set IDAC_cy_psoc4_idac__CSD_IDAC_SHIFT, 0
.set IDAC_cy_psoc4_idac__CSD_TRIM1, CYREG_CSD_TRIM1
.set IDAC_cy_psoc4_idac__CSD_TRIM1_SHIFT, 0
.set IDAC_cy_psoc4_idac__CSD_TRIM2, CYREG_CSD_TRIM2
.set IDAC_cy_psoc4_idac__CSD_TRIM2_SHIFT, 0
.set IDAC_cy_psoc4_idac__IDAC_NUMBER, 1
.set IDAC_cy_psoc4_idac__POLARITY, CYREG_CSD_CONFIG
.set IDAC_cy_psoc4_idac__POLARITY_SHIFT, 16

/* PIN_BLUE */
.set PIN_BLUE__0__DR, CYREG_GPIO_PRT3_DR
.set PIN_BLUE__0__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set PIN_BLUE__0__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set PIN_BLUE__0__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set PIN_BLUE__0__HSIOM, CYREG_HSIOM_PORT_SEL3
.set PIN_BLUE__0__HSIOM_MASK, 0xF0000000
.set PIN_BLUE__0__HSIOM_SHIFT, 28
.set PIN_BLUE__0__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set PIN_BLUE__0__INTR, CYREG_GPIO_PRT3_INTR
.set PIN_BLUE__0__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set PIN_BLUE__0__INTSTAT, CYREG_GPIO_PRT3_INTR
.set PIN_BLUE__0__MASK, 0x80
.set PIN_BLUE__0__OUT_SEL, CYREG_UDB_PA3_CFG10
.set PIN_BLUE__0__OUT_SEL_SHIFT, 14
.set PIN_BLUE__0__OUT_SEL_VAL, -1
.set PIN_BLUE__0__PA__CFG0, CYREG_UDB_PA3_CFG0
.set PIN_BLUE__0__PA__CFG1, CYREG_UDB_PA3_CFG1
.set PIN_BLUE__0__PA__CFG10, CYREG_UDB_PA3_CFG10
.set PIN_BLUE__0__PA__CFG11, CYREG_UDB_PA3_CFG11
.set PIN_BLUE__0__PA__CFG12, CYREG_UDB_PA3_CFG12
.set PIN_BLUE__0__PA__CFG13, CYREG_UDB_PA3_CFG13
.set PIN_BLUE__0__PA__CFG14, CYREG_UDB_PA3_CFG14
.set PIN_BLUE__0__PA__CFG2, CYREG_UDB_PA3_CFG2
.set PIN_BLUE__0__PA__CFG3, CYREG_UDB_PA3_CFG3
.set PIN_BLUE__0__PA__CFG4, CYREG_UDB_PA3_CFG4
.set PIN_BLUE__0__PA__CFG5, CYREG_UDB_PA3_CFG5
.set PIN_BLUE__0__PA__CFG6, CYREG_UDB_PA3_CFG6
.set PIN_BLUE__0__PA__CFG7, CYREG_UDB_PA3_CFG7
.set PIN_BLUE__0__PA__CFG8, CYREG_UDB_PA3_CFG8
.set PIN_BLUE__0__PA__CFG9, CYREG_UDB_PA3_CFG9
.set PIN_BLUE__0__PC, CYREG_GPIO_PRT3_PC
.set PIN_BLUE__0__PC2, CYREG_GPIO_PRT3_PC2
.set PIN_BLUE__0__PORT, 3
.set PIN_BLUE__0__PS, CYREG_GPIO_PRT3_PS
.set PIN_BLUE__0__SHIFT, 7
.set PIN_BLUE__DR, CYREG_GPIO_PRT3_DR
.set PIN_BLUE__DR_CLR, CYREG_GPIO_PRT3_DR_CLR
.set PIN_BLUE__DR_INV, CYREG_GPIO_PRT3_DR_INV
.set PIN_BLUE__DR_SET, CYREG_GPIO_PRT3_DR_SET
.set PIN_BLUE__INTCFG, CYREG_GPIO_PRT3_INTR_CFG
.set PIN_BLUE__INTR, CYREG_GPIO_PRT3_INTR
.set PIN_BLUE__INTR_CFG, CYREG_GPIO_PRT3_INTR_CFG
.set PIN_BLUE__INTSTAT, CYREG_GPIO_PRT3_INTR
.set PIN_BLUE__MASK, 0x80
.set PIN_BLUE__PA__CFG0, CYREG_UDB_PA3_CFG0
.set PIN_BLUE__PA__CFG1, CYREG_UDB_PA3_CFG1
.set PIN_BLUE__PA__CFG10, CYREG_UDB_PA3_CFG10
.set PIN_BLUE__PA__CFG11, CYREG_UDB_PA3_CFG11
.set PIN_BLUE__PA__CFG12, CYREG_UDB_PA3_CFG12
.set PIN_BLUE__PA__CFG13, CYREG_UDB_PA3_CFG13
.set PIN_BLUE__PA__CFG14, CYREG_UDB_PA3_CFG14
.set PIN_BLUE__PA__CFG2, CYREG_UDB_PA3_CFG2
.set PIN_BLUE__PA__CFG3, CYREG_UDB_PA3_CFG3
.set PIN_BLUE__PA__CFG4, CYREG_UDB_PA3_CFG4
.set PIN_BLUE__PA__CFG5, CYREG_UDB_PA3_CFG5
.set PIN_BLUE__PA__CFG6, CYREG_UDB_PA3_CFG6
.set PIN_BLUE__PA__CFG7, CYREG_UDB_PA3_CFG7
.set PIN_BLUE__PA__CFG8, CYREG_UDB_PA3_CFG8
.set PIN_BLUE__PA__CFG9, CYREG_UDB_PA3_CFG9
.set PIN_BLUE__PC, CYREG_GPIO_PRT3_PC
.set PIN_BLUE__PC2, CYREG_GPIO_PRT3_PC2
.set PIN_BLUE__PORT, 3
.set PIN_BLUE__PS, CYREG_GPIO_PRT3_PS
.set PIN_BLUE__SHIFT, 7

/* PIN_RED */
.set PIN_RED__0__DR, CYREG_GPIO_PRT2_DR
.set PIN_RED__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set PIN_RED__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set PIN_RED__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set PIN_RED__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set PIN_RED__0__HSIOM_MASK, 0x0F000000
.set PIN_RED__0__HSIOM_SHIFT, 24
.set PIN_RED__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set PIN_RED__0__INTR, CYREG_GPIO_PRT2_INTR
.set PIN_RED__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set PIN_RED__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set PIN_RED__0__MASK, 0x40
.set PIN_RED__0__OUT_SEL, CYREG_UDB_PA2_CFG10
.set PIN_RED__0__OUT_SEL_SHIFT, 12
.set PIN_RED__0__OUT_SEL_VAL, 1
.set PIN_RED__0__PA__CFG0, CYREG_UDB_PA2_CFG0
.set PIN_RED__0__PA__CFG1, CYREG_UDB_PA2_CFG1
.set PIN_RED__0__PA__CFG10, CYREG_UDB_PA2_CFG10
.set PIN_RED__0__PA__CFG11, CYREG_UDB_PA2_CFG11
.set PIN_RED__0__PA__CFG12, CYREG_UDB_PA2_CFG12
.set PIN_RED__0__PA__CFG13, CYREG_UDB_PA2_CFG13
.set PIN_RED__0__PA__CFG14, CYREG_UDB_PA2_CFG14
.set PIN_RED__0__PA__CFG2, CYREG_UDB_PA2_CFG2
.set PIN_RED__0__PA__CFG3, CYREG_UDB_PA2_CFG3
.set PIN_RED__0__PA__CFG4, CYREG_UDB_PA2_CFG4
.set PIN_RED__0__PA__CFG5, CYREG_UDB_PA2_CFG5
.set PIN_RED__0__PA__CFG6, CYREG_UDB_PA2_CFG6
.set PIN_RED__0__PA__CFG7, CYREG_UDB_PA2_CFG7
.set PIN_RED__0__PA__CFG8, CYREG_UDB_PA2_CFG8
.set PIN_RED__0__PA__CFG9, CYREG_UDB_PA2_CFG9
.set PIN_RED__0__PC, CYREG_GPIO_PRT2_PC
.set PIN_RED__0__PC2, CYREG_GPIO_PRT2_PC2
.set PIN_RED__0__PORT, 2
.set PIN_RED__0__PS, CYREG_GPIO_PRT2_PS
.set PIN_RED__0__SHIFT, 6
.set PIN_RED__DR, CYREG_GPIO_PRT2_DR
.set PIN_RED__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set PIN_RED__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set PIN_RED__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set PIN_RED__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set PIN_RED__INTR, CYREG_GPIO_PRT2_INTR
.set PIN_RED__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set PIN_RED__INTSTAT, CYREG_GPIO_PRT2_INTR
.set PIN_RED__MASK, 0x40
.set PIN_RED__PA__CFG0, CYREG_UDB_PA2_CFG0
.set PIN_RED__PA__CFG1, CYREG_UDB_PA2_CFG1
.set PIN_RED__PA__CFG10, CYREG_UDB_PA2_CFG10
.set PIN_RED__PA__CFG11, CYREG_UDB_PA2_CFG11
.set PIN_RED__PA__CFG12, CYREG_UDB_PA2_CFG12
.set PIN_RED__PA__CFG13, CYREG_UDB_PA2_CFG13
.set PIN_RED__PA__CFG14, CYREG_UDB_PA2_CFG14
.set PIN_RED__PA__CFG2, CYREG_UDB_PA2_CFG2
.set PIN_RED__PA__CFG3, CYREG_UDB_PA2_CFG3
.set PIN_RED__PA__CFG4, CYREG_UDB_PA2_CFG4
.set PIN_RED__PA__CFG5, CYREG_UDB_PA2_CFG5
.set PIN_RED__PA__CFG6, CYREG_UDB_PA2_CFG6
.set PIN_RED__PA__CFG7, CYREG_UDB_PA2_CFG7
.set PIN_RED__PA__CFG8, CYREG_UDB_PA2_CFG8
.set PIN_RED__PA__CFG9, CYREG_UDB_PA2_CFG9
.set PIN_RED__PC, CYREG_GPIO_PRT2_PC
.set PIN_RED__PC2, CYREG_GPIO_PRT2_PC2
.set PIN_RED__PORT, 2
.set PIN_RED__PS, CYREG_GPIO_PRT2_PS
.set PIN_RED__SHIFT, 6

/* PWM_BLUE */
.set PWM_BLUE_cy_m0s8_tcpwm_1__CC, CYREG_TCPWM_CNT3_CC
.set PWM_BLUE_cy_m0s8_tcpwm_1__CC_BUFF, CYREG_TCPWM_CNT3_CC_BUFF
.set PWM_BLUE_cy_m0s8_tcpwm_1__COUNTER, CYREG_TCPWM_CNT3_COUNTER
.set PWM_BLUE_cy_m0s8_tcpwm_1__CTRL, CYREG_TCPWM_CNT3_CTRL
.set PWM_BLUE_cy_m0s8_tcpwm_1__INTR, CYREG_TCPWM_CNT3_INTR
.set PWM_BLUE_cy_m0s8_tcpwm_1__INTR_MASK, CYREG_TCPWM_CNT3_INTR_MASK
.set PWM_BLUE_cy_m0s8_tcpwm_1__INTR_MASKED, CYREG_TCPWM_CNT3_INTR_MASKED
.set PWM_BLUE_cy_m0s8_tcpwm_1__INTR_SET, CYREG_TCPWM_CNT3_INTR_SET
.set PWM_BLUE_cy_m0s8_tcpwm_1__PERIOD, CYREG_TCPWM_CNT3_PERIOD
.set PWM_BLUE_cy_m0s8_tcpwm_1__PERIOD_BUFF, CYREG_TCPWM_CNT3_PERIOD_BUFF
.set PWM_BLUE_cy_m0s8_tcpwm_1__STATUS, CYREG_TCPWM_CNT3_STATUS
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMD, CYREG_TCPWM_CMD
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK, 0x08
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT, 3
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK, 0x800
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT, 11
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK, 0x8000000
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT, 27
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK, 0x80000
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT, 19
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL, CYREG_TCPWM_CTRL
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK, 0x08
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT, 3
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE, CYREG_TCPWM_INTR_CAUSE
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK, 0x08
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT, 3
.set PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_NUMBER, 3
.set PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL0, CYREG_TCPWM_CNT3_TR_CTRL0
.set PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL1, CYREG_TCPWM_CNT3_TR_CTRL1
.set PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL2, CYREG_TCPWM_CNT3_TR_CTRL2

/* PWM_RED */
.set PWM_RED_cy_m0s8_tcpwm_1__CC, CYREG_TCPWM_CNT0_CC
.set PWM_RED_cy_m0s8_tcpwm_1__CC_BUFF, CYREG_TCPWM_CNT0_CC_BUFF
.set PWM_RED_cy_m0s8_tcpwm_1__COUNTER, CYREG_TCPWM_CNT0_COUNTER
.set PWM_RED_cy_m0s8_tcpwm_1__CTRL, CYREG_TCPWM_CNT0_CTRL
.set PWM_RED_cy_m0s8_tcpwm_1__INTR, CYREG_TCPWM_CNT0_INTR
.set PWM_RED_cy_m0s8_tcpwm_1__INTR_MASK, CYREG_TCPWM_CNT0_INTR_MASK
.set PWM_RED_cy_m0s8_tcpwm_1__INTR_MASKED, CYREG_TCPWM_CNT0_INTR_MASKED
.set PWM_RED_cy_m0s8_tcpwm_1__INTR_SET, CYREG_TCPWM_CNT0_INTR_SET
.set PWM_RED_cy_m0s8_tcpwm_1__PERIOD, CYREG_TCPWM_CNT0_PERIOD
.set PWM_RED_cy_m0s8_tcpwm_1__PERIOD_BUFF, CYREG_TCPWM_CNT0_PERIOD_BUFF
.set PWM_RED_cy_m0s8_tcpwm_1__STATUS, CYREG_TCPWM_CNT0_STATUS
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMD, CYREG_TCPWM_CMD
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK, 0x01
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT, 0
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK, 0x100
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT, 8
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK, 0x1000000
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT, 24
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK, 0x10000
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT, 16
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL, CYREG_TCPWM_CTRL
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK, 0x01
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT, 0
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE, CYREG_TCPWM_INTR_CAUSE
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK, 0x01
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT, 0
.set PWM_RED_cy_m0s8_tcpwm_1__TCPWM_NUMBER, 0
.set PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL0, CYREG_TCPWM_CNT0_TR_CTRL0
.set PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL1, CYREG_TCPWM_CNT0_TR_CTRL1
.set PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL2, CYREG_TCPWM_CNT0_TR_CTRL2

/* SENSOR_1 */
.set SENSOR_1__0__DR, CYREG_GPIO_PRT0_DR
.set SENSOR_1__0__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set SENSOR_1__0__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set SENSOR_1__0__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set SENSOR_1__0__HSIOM, CYREG_HSIOM_PORT_SEL0
.set SENSOR_1__0__HSIOM_MASK, 0x00F00000
.set SENSOR_1__0__HSIOM_SHIFT, 20
.set SENSOR_1__0__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set SENSOR_1__0__INTR, CYREG_GPIO_PRT0_INTR
.set SENSOR_1__0__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set SENSOR_1__0__INTSTAT, CYREG_GPIO_PRT0_INTR
.set SENSOR_1__0__MASK, 0x20
.set SENSOR_1__0__OUT_SEL, CYREG_UDB_PA0_CFG10
.set SENSOR_1__0__OUT_SEL_SHIFT, 10
.set SENSOR_1__0__OUT_SEL_VAL, 0
.set SENSOR_1__0__PA__CFG0, CYREG_UDB_PA0_CFG0
.set SENSOR_1__0__PA__CFG1, CYREG_UDB_PA0_CFG1
.set SENSOR_1__0__PA__CFG10, CYREG_UDB_PA0_CFG10
.set SENSOR_1__0__PA__CFG11, CYREG_UDB_PA0_CFG11
.set SENSOR_1__0__PA__CFG12, CYREG_UDB_PA0_CFG12
.set SENSOR_1__0__PA__CFG13, CYREG_UDB_PA0_CFG13
.set SENSOR_1__0__PA__CFG14, CYREG_UDB_PA0_CFG14
.set SENSOR_1__0__PA__CFG2, CYREG_UDB_PA0_CFG2
.set SENSOR_1__0__PA__CFG3, CYREG_UDB_PA0_CFG3
.set SENSOR_1__0__PA__CFG4, CYREG_UDB_PA0_CFG4
.set SENSOR_1__0__PA__CFG5, CYREG_UDB_PA0_CFG5
.set SENSOR_1__0__PA__CFG6, CYREG_UDB_PA0_CFG6
.set SENSOR_1__0__PA__CFG7, CYREG_UDB_PA0_CFG7
.set SENSOR_1__0__PA__CFG8, CYREG_UDB_PA0_CFG8
.set SENSOR_1__0__PA__CFG9, CYREG_UDB_PA0_CFG9
.set SENSOR_1__0__PC, CYREG_GPIO_PRT0_PC
.set SENSOR_1__0__PC2, CYREG_GPIO_PRT0_PC2
.set SENSOR_1__0__PORT, 0
.set SENSOR_1__0__PS, CYREG_GPIO_PRT0_PS
.set SENSOR_1__0__SHIFT, 5
.set SENSOR_1__DR, CYREG_GPIO_PRT0_DR
.set SENSOR_1__DR_CLR, CYREG_GPIO_PRT0_DR_CLR
.set SENSOR_1__DR_INV, CYREG_GPIO_PRT0_DR_INV
.set SENSOR_1__DR_SET, CYREG_GPIO_PRT0_DR_SET
.set SENSOR_1__INTCFG, CYREG_GPIO_PRT0_INTR_CFG
.set SENSOR_1__INTR, CYREG_GPIO_PRT0_INTR
.set SENSOR_1__INTR_CFG, CYREG_GPIO_PRT0_INTR_CFG
.set SENSOR_1__INTSTAT, CYREG_GPIO_PRT0_INTR
.set SENSOR_1__MASK, 0x20
.set SENSOR_1__PA__CFG0, CYREG_UDB_PA0_CFG0
.set SENSOR_1__PA__CFG1, CYREG_UDB_PA0_CFG1
.set SENSOR_1__PA__CFG10, CYREG_UDB_PA0_CFG10
.set SENSOR_1__PA__CFG11, CYREG_UDB_PA0_CFG11
.set SENSOR_1__PA__CFG12, CYREG_UDB_PA0_CFG12
.set SENSOR_1__PA__CFG13, CYREG_UDB_PA0_CFG13
.set SENSOR_1__PA__CFG14, CYREG_UDB_PA0_CFG14
.set SENSOR_1__PA__CFG2, CYREG_UDB_PA0_CFG2
.set SENSOR_1__PA__CFG3, CYREG_UDB_PA0_CFG3
.set SENSOR_1__PA__CFG4, CYREG_UDB_PA0_CFG4
.set SENSOR_1__PA__CFG5, CYREG_UDB_PA0_CFG5
.set SENSOR_1__PA__CFG6, CYREG_UDB_PA0_CFG6
.set SENSOR_1__PA__CFG7, CYREG_UDB_PA0_CFG7
.set SENSOR_1__PA__CFG8, CYREG_UDB_PA0_CFG8
.set SENSOR_1__PA__CFG9, CYREG_UDB_PA0_CFG9
.set SENSOR_1__PC, CYREG_GPIO_PRT0_PC
.set SENSOR_1__PC2, CYREG_GPIO_PRT0_PC2
.set SENSOR_1__PORT, 0
.set SENSOR_1__PS, CYREG_GPIO_PRT0_PS
.set SENSOR_1__SHIFT, 5

/* SENSOR_2 */
.set SENSOR_2__0__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_2__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_2__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_2__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_2__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set SENSOR_2__0__HSIOM_MASK, 0x0000000F
.set SENSOR_2__0__HSIOM_SHIFT, 0
.set SENSOR_2__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_2__0__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_2__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_2__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_2__0__MASK, 0x01
.set SENSOR_2__0__OUT_SEL, CYREG_UDB_PA1_CFG10
.set SENSOR_2__0__OUT_SEL_SHIFT, 0
.set SENSOR_2__0__OUT_SEL_VAL, 3
.set SENSOR_2__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_2__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_2__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_2__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_2__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_2__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_2__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_2__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_2__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_2__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_2__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_2__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_2__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_2__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_2__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_2__0__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_2__0__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_2__0__PORT, 1
.set SENSOR_2__0__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_2__0__SHIFT, 0
.set SENSOR_2__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_2__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_2__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_2__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_2__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_2__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_2__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_2__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_2__MASK, 0x01
.set SENSOR_2__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_2__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_2__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_2__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_2__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_2__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_2__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_2__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_2__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_2__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_2__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_2__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_2__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_2__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_2__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_2__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_2__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_2__PORT, 1
.set SENSOR_2__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_2__SHIFT, 0

/* SENSOR_3 */
.set SENSOR_3__0__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_3__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_3__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_3__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_3__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set SENSOR_3__0__HSIOM_MASK, 0x000000F0
.set SENSOR_3__0__HSIOM_SHIFT, 4
.set SENSOR_3__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_3__0__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_3__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_3__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_3__0__MASK, 0x02
.set SENSOR_3__0__OUT_SEL, CYREG_UDB_PA1_CFG10
.set SENSOR_3__0__OUT_SEL_SHIFT, 2
.set SENSOR_3__0__OUT_SEL_VAL, 3
.set SENSOR_3__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_3__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_3__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_3__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_3__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_3__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_3__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_3__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_3__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_3__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_3__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_3__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_3__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_3__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_3__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_3__0__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_3__0__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_3__0__PORT, 1
.set SENSOR_3__0__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_3__0__SHIFT, 1
.set SENSOR_3__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_3__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_3__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_3__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_3__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_3__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_3__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_3__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_3__MASK, 0x02
.set SENSOR_3__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_3__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_3__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_3__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_3__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_3__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_3__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_3__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_3__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_3__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_3__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_3__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_3__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_3__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_3__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_3__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_3__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_3__PORT, 1
.set SENSOR_3__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_3__SHIFT, 1

/* SENSOR_4 */
.set SENSOR_4__0__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_4__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_4__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_4__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_4__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set SENSOR_4__0__HSIOM_MASK, 0x00000F00
.set SENSOR_4__0__HSIOM_SHIFT, 8
.set SENSOR_4__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_4__0__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_4__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_4__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_4__0__MASK, 0x04
.set SENSOR_4__0__OUT_SEL, CYREG_UDB_PA1_CFG10
.set SENSOR_4__0__OUT_SEL_SHIFT, 4
.set SENSOR_4__0__OUT_SEL_VAL, 3
.set SENSOR_4__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_4__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_4__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_4__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_4__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_4__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_4__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_4__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_4__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_4__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_4__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_4__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_4__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_4__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_4__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_4__0__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_4__0__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_4__0__PORT, 1
.set SENSOR_4__0__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_4__0__SHIFT, 2
.set SENSOR_4__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_4__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_4__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_4__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_4__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_4__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_4__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_4__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_4__MASK, 0x04
.set SENSOR_4__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_4__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_4__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_4__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_4__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_4__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_4__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_4__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_4__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_4__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_4__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_4__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_4__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_4__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_4__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_4__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_4__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_4__PORT, 1
.set SENSOR_4__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_4__SHIFT, 2

/* SENSOR_5 */
.set SENSOR_5__0__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_5__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_5__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_5__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_5__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set SENSOR_5__0__HSIOM_MASK, 0x0000F000
.set SENSOR_5__0__HSIOM_SHIFT, 12
.set SENSOR_5__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_5__0__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_5__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_5__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_5__0__MASK, 0x08
.set SENSOR_5__0__OUT_SEL, CYREG_UDB_PA1_CFG10
.set SENSOR_5__0__OUT_SEL_SHIFT, 6
.set SENSOR_5__0__OUT_SEL_VAL, 3
.set SENSOR_5__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_5__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_5__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_5__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_5__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_5__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_5__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_5__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_5__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_5__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_5__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_5__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_5__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_5__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_5__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_5__0__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_5__0__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_5__0__PORT, 1
.set SENSOR_5__0__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_5__0__SHIFT, 3
.set SENSOR_5__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_5__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_5__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_5__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_5__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_5__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_5__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_5__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_5__MASK, 0x08
.set SENSOR_5__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_5__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_5__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_5__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_5__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_5__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_5__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_5__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_5__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_5__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_5__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_5__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_5__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_5__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_5__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_5__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_5__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_5__PORT, 1
.set SENSOR_5__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_5__SHIFT, 3

/* SENSOR_6 */
.set SENSOR_6__0__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_6__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_6__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_6__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_6__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set SENSOR_6__0__HSIOM_MASK, 0xF0000000
.set SENSOR_6__0__HSIOM_SHIFT, 28
.set SENSOR_6__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_6__0__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_6__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_6__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_6__0__MASK, 0x80
.set SENSOR_6__0__OUT_SEL, CYREG_UDB_PA1_CFG10
.set SENSOR_6__0__OUT_SEL_SHIFT, 14
.set SENSOR_6__0__OUT_SEL_VAL, 0
.set SENSOR_6__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_6__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_6__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_6__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_6__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_6__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_6__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_6__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_6__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_6__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_6__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_6__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_6__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_6__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_6__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_6__0__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_6__0__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_6__0__PORT, 1
.set SENSOR_6__0__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_6__0__SHIFT, 7
.set SENSOR_6__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_6__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_6__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_6__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_6__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_6__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_6__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_6__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_6__MASK, 0x80
.set SENSOR_6__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_6__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_6__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_6__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_6__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_6__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_6__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_6__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_6__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_6__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_6__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_6__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_6__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_6__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_6__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_6__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_6__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_6__PORT, 1
.set SENSOR_6__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_6__SHIFT, 7

/* SENSOR_7 */
.set SENSOR_7__0__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_7__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_7__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_7__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_7__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set SENSOR_7__0__HSIOM_MASK, 0x0F000000
.set SENSOR_7__0__HSIOM_SHIFT, 24
.set SENSOR_7__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_7__0__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_7__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_7__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_7__0__MASK, 0x40
.set SENSOR_7__0__OUT_SEL, CYREG_UDB_PA1_CFG10
.set SENSOR_7__0__OUT_SEL_SHIFT, 12
.set SENSOR_7__0__OUT_SEL_VAL, 0
.set SENSOR_7__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_7__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_7__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_7__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_7__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_7__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_7__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_7__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_7__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_7__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_7__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_7__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_7__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_7__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_7__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_7__0__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_7__0__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_7__0__PORT, 1
.set SENSOR_7__0__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_7__0__SHIFT, 6
.set SENSOR_7__DR, CYREG_GPIO_PRT1_DR
.set SENSOR_7__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set SENSOR_7__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set SENSOR_7__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set SENSOR_7__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_7__INTR, CYREG_GPIO_PRT1_INTR
.set SENSOR_7__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set SENSOR_7__INTSTAT, CYREG_GPIO_PRT1_INTR
.set SENSOR_7__MASK, 0x40
.set SENSOR_7__PA__CFG0, CYREG_UDB_PA1_CFG0
.set SENSOR_7__PA__CFG1, CYREG_UDB_PA1_CFG1
.set SENSOR_7__PA__CFG10, CYREG_UDB_PA1_CFG10
.set SENSOR_7__PA__CFG11, CYREG_UDB_PA1_CFG11
.set SENSOR_7__PA__CFG12, CYREG_UDB_PA1_CFG12
.set SENSOR_7__PA__CFG13, CYREG_UDB_PA1_CFG13
.set SENSOR_7__PA__CFG14, CYREG_UDB_PA1_CFG14
.set SENSOR_7__PA__CFG2, CYREG_UDB_PA1_CFG2
.set SENSOR_7__PA__CFG3, CYREG_UDB_PA1_CFG3
.set SENSOR_7__PA__CFG4, CYREG_UDB_PA1_CFG4
.set SENSOR_7__PA__CFG5, CYREG_UDB_PA1_CFG5
.set SENSOR_7__PA__CFG6, CYREG_UDB_PA1_CFG6
.set SENSOR_7__PA__CFG7, CYREG_UDB_PA1_CFG7
.set SENSOR_7__PA__CFG8, CYREG_UDB_PA1_CFG8
.set SENSOR_7__PA__CFG9, CYREG_UDB_PA1_CFG9
.set SENSOR_7__PC, CYREG_GPIO_PRT1_PC
.set SENSOR_7__PC2, CYREG_GPIO_PRT1_PC2
.set SENSOR_7__PORT, 1
.set SENSOR_7__PS, CYREG_GPIO_PRT1_PS
.set SENSOR_7__SHIFT, 6

/* SENSOR_8 */
.set SENSOR_8__0__DR, CYREG_GPIO_PRT2_DR
.set SENSOR_8__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SENSOR_8__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SENSOR_8__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SENSOR_8__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set SENSOR_8__0__HSIOM_MASK, 0x0000000F
.set SENSOR_8__0__HSIOM_SHIFT, 0
.set SENSOR_8__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_8__0__INTR, CYREG_GPIO_PRT2_INTR
.set SENSOR_8__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_8__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SENSOR_8__0__MASK, 0x01
.set SENSOR_8__0__OUT_SEL, CYREG_UDB_PA2_CFG10
.set SENSOR_8__0__OUT_SEL_SHIFT, 0
.set SENSOR_8__0__OUT_SEL_VAL, 1
.set SENSOR_8__0__PA__CFG0, CYREG_UDB_PA2_CFG0
.set SENSOR_8__0__PA__CFG1, CYREG_UDB_PA2_CFG1
.set SENSOR_8__0__PA__CFG10, CYREG_UDB_PA2_CFG10
.set SENSOR_8__0__PA__CFG11, CYREG_UDB_PA2_CFG11
.set SENSOR_8__0__PA__CFG12, CYREG_UDB_PA2_CFG12
.set SENSOR_8__0__PA__CFG13, CYREG_UDB_PA2_CFG13
.set SENSOR_8__0__PA__CFG14, CYREG_UDB_PA2_CFG14
.set SENSOR_8__0__PA__CFG2, CYREG_UDB_PA2_CFG2
.set SENSOR_8__0__PA__CFG3, CYREG_UDB_PA2_CFG3
.set SENSOR_8__0__PA__CFG4, CYREG_UDB_PA2_CFG4
.set SENSOR_8__0__PA__CFG5, CYREG_UDB_PA2_CFG5
.set SENSOR_8__0__PA__CFG6, CYREG_UDB_PA2_CFG6
.set SENSOR_8__0__PA__CFG7, CYREG_UDB_PA2_CFG7
.set SENSOR_8__0__PA__CFG8, CYREG_UDB_PA2_CFG8
.set SENSOR_8__0__PA__CFG9, CYREG_UDB_PA2_CFG9
.set SENSOR_8__0__PC, CYREG_GPIO_PRT2_PC
.set SENSOR_8__0__PC2, CYREG_GPIO_PRT2_PC2
.set SENSOR_8__0__PORT, 2
.set SENSOR_8__0__PS, CYREG_GPIO_PRT2_PS
.set SENSOR_8__0__SHIFT, 0
.set SENSOR_8__DR, CYREG_GPIO_PRT2_DR
.set SENSOR_8__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SENSOR_8__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SENSOR_8__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SENSOR_8__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_8__INTR, CYREG_GPIO_PRT2_INTR
.set SENSOR_8__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_8__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SENSOR_8__MASK, 0x01
.set SENSOR_8__PA__CFG0, CYREG_UDB_PA2_CFG0
.set SENSOR_8__PA__CFG1, CYREG_UDB_PA2_CFG1
.set SENSOR_8__PA__CFG10, CYREG_UDB_PA2_CFG10
.set SENSOR_8__PA__CFG11, CYREG_UDB_PA2_CFG11
.set SENSOR_8__PA__CFG12, CYREG_UDB_PA2_CFG12
.set SENSOR_8__PA__CFG13, CYREG_UDB_PA2_CFG13
.set SENSOR_8__PA__CFG14, CYREG_UDB_PA2_CFG14
.set SENSOR_8__PA__CFG2, CYREG_UDB_PA2_CFG2
.set SENSOR_8__PA__CFG3, CYREG_UDB_PA2_CFG3
.set SENSOR_8__PA__CFG4, CYREG_UDB_PA2_CFG4
.set SENSOR_8__PA__CFG5, CYREG_UDB_PA2_CFG5
.set SENSOR_8__PA__CFG6, CYREG_UDB_PA2_CFG6
.set SENSOR_8__PA__CFG7, CYREG_UDB_PA2_CFG7
.set SENSOR_8__PA__CFG8, CYREG_UDB_PA2_CFG8
.set SENSOR_8__PA__CFG9, CYREG_UDB_PA2_CFG9
.set SENSOR_8__PC, CYREG_GPIO_PRT2_PC
.set SENSOR_8__PC2, CYREG_GPIO_PRT2_PC2
.set SENSOR_8__PORT, 2
.set SENSOR_8__PS, CYREG_GPIO_PRT2_PS
.set SENSOR_8__SHIFT, 0

/* SENSOR_9 */
.set SENSOR_9__0__DR, CYREG_GPIO_PRT2_DR
.set SENSOR_9__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SENSOR_9__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SENSOR_9__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SENSOR_9__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set SENSOR_9__0__HSIOM_MASK, 0x000000F0
.set SENSOR_9__0__HSIOM_SHIFT, 4
.set SENSOR_9__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_9__0__INTR, CYREG_GPIO_PRT2_INTR
.set SENSOR_9__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_9__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SENSOR_9__0__MASK, 0x02
.set SENSOR_9__0__OUT_SEL, CYREG_UDB_PA2_CFG10
.set SENSOR_9__0__OUT_SEL_SHIFT, 2
.set SENSOR_9__0__OUT_SEL_VAL, 1
.set SENSOR_9__0__PA__CFG0, CYREG_UDB_PA2_CFG0
.set SENSOR_9__0__PA__CFG1, CYREG_UDB_PA2_CFG1
.set SENSOR_9__0__PA__CFG10, CYREG_UDB_PA2_CFG10
.set SENSOR_9__0__PA__CFG11, CYREG_UDB_PA2_CFG11
.set SENSOR_9__0__PA__CFG12, CYREG_UDB_PA2_CFG12
.set SENSOR_9__0__PA__CFG13, CYREG_UDB_PA2_CFG13
.set SENSOR_9__0__PA__CFG14, CYREG_UDB_PA2_CFG14
.set SENSOR_9__0__PA__CFG2, CYREG_UDB_PA2_CFG2
.set SENSOR_9__0__PA__CFG3, CYREG_UDB_PA2_CFG3
.set SENSOR_9__0__PA__CFG4, CYREG_UDB_PA2_CFG4
.set SENSOR_9__0__PA__CFG5, CYREG_UDB_PA2_CFG5
.set SENSOR_9__0__PA__CFG6, CYREG_UDB_PA2_CFG6
.set SENSOR_9__0__PA__CFG7, CYREG_UDB_PA2_CFG7
.set SENSOR_9__0__PA__CFG8, CYREG_UDB_PA2_CFG8
.set SENSOR_9__0__PA__CFG9, CYREG_UDB_PA2_CFG9
.set SENSOR_9__0__PC, CYREG_GPIO_PRT2_PC
.set SENSOR_9__0__PC2, CYREG_GPIO_PRT2_PC2
.set SENSOR_9__0__PORT, 2
.set SENSOR_9__0__PS, CYREG_GPIO_PRT2_PS
.set SENSOR_9__0__SHIFT, 1
.set SENSOR_9__DR, CYREG_GPIO_PRT2_DR
.set SENSOR_9__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SENSOR_9__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SENSOR_9__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SENSOR_9__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_9__INTR, CYREG_GPIO_PRT2_INTR
.set SENSOR_9__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SENSOR_9__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SENSOR_9__MASK, 0x02
.set SENSOR_9__PA__CFG0, CYREG_UDB_PA2_CFG0
.set SENSOR_9__PA__CFG1, CYREG_UDB_PA2_CFG1
.set SENSOR_9__PA__CFG10, CYREG_UDB_PA2_CFG10
.set SENSOR_9__PA__CFG11, CYREG_UDB_PA2_CFG11
.set SENSOR_9__PA__CFG12, CYREG_UDB_PA2_CFG12
.set SENSOR_9__PA__CFG13, CYREG_UDB_PA2_CFG13
.set SENSOR_9__PA__CFG14, CYREG_UDB_PA2_CFG14
.set SENSOR_9__PA__CFG2, CYREG_UDB_PA2_CFG2
.set SENSOR_9__PA__CFG3, CYREG_UDB_PA2_CFG3
.set SENSOR_9__PA__CFG4, CYREG_UDB_PA2_CFG4
.set SENSOR_9__PA__CFG5, CYREG_UDB_PA2_CFG5
.set SENSOR_9__PA__CFG6, CYREG_UDB_PA2_CFG6
.set SENSOR_9__PA__CFG7, CYREG_UDB_PA2_CFG7
.set SENSOR_9__PA__CFG8, CYREG_UDB_PA2_CFG8
.set SENSOR_9__PA__CFG9, CYREG_UDB_PA2_CFG9
.set SENSOR_9__PC, CYREG_GPIO_PRT2_PC
.set SENSOR_9__PC2, CYREG_GPIO_PRT2_PC2
.set SENSOR_9__PORT, 2
.set SENSOR_9__PS, CYREG_GPIO_PRT2_PS
.set SENSOR_9__SHIFT, 1

/* SW */
.set SW__0__DR, CYREG_GPIO_PRT2_DR
.set SW__0__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SW__0__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SW__0__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SW__0__HSIOM, CYREG_HSIOM_PORT_SEL2
.set SW__0__HSIOM_MASK, 0xF0000000
.set SW__0__HSIOM_SHIFT, 28
.set SW__0__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SW__0__INTR, CYREG_GPIO_PRT2_INTR
.set SW__0__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SW__0__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SW__0__MASK, 0x80
.set SW__0__PA__CFG0, CYREG_UDB_PA2_CFG0
.set SW__0__PA__CFG1, CYREG_UDB_PA2_CFG1
.set SW__0__PA__CFG10, CYREG_UDB_PA2_CFG10
.set SW__0__PA__CFG11, CYREG_UDB_PA2_CFG11
.set SW__0__PA__CFG12, CYREG_UDB_PA2_CFG12
.set SW__0__PA__CFG13, CYREG_UDB_PA2_CFG13
.set SW__0__PA__CFG14, CYREG_UDB_PA2_CFG14
.set SW__0__PA__CFG2, CYREG_UDB_PA2_CFG2
.set SW__0__PA__CFG3, CYREG_UDB_PA2_CFG3
.set SW__0__PA__CFG4, CYREG_UDB_PA2_CFG4
.set SW__0__PA__CFG5, CYREG_UDB_PA2_CFG5
.set SW__0__PA__CFG6, CYREG_UDB_PA2_CFG6
.set SW__0__PA__CFG7, CYREG_UDB_PA2_CFG7
.set SW__0__PA__CFG8, CYREG_UDB_PA2_CFG8
.set SW__0__PA__CFG9, CYREG_UDB_PA2_CFG9
.set SW__0__PC, CYREG_GPIO_PRT2_PC
.set SW__0__PC2, CYREG_GPIO_PRT2_PC2
.set SW__0__PORT, 2
.set SW__0__PS, CYREG_GPIO_PRT2_PS
.set SW__0__SHIFT, 7
.set SW__DR, CYREG_GPIO_PRT2_DR
.set SW__DR_CLR, CYREG_GPIO_PRT2_DR_CLR
.set SW__DR_INV, CYREG_GPIO_PRT2_DR_INV
.set SW__DR_SET, CYREG_GPIO_PRT2_DR_SET
.set SW__INTCFG, CYREG_GPIO_PRT2_INTR_CFG
.set SW__INTR, CYREG_GPIO_PRT2_INTR
.set SW__INTR_CFG, CYREG_GPIO_PRT2_INTR_CFG
.set SW__INTSTAT, CYREG_GPIO_PRT2_INTR
.set SW__MASK, 0x80
.set SW__PA__CFG0, CYREG_UDB_PA2_CFG0
.set SW__PA__CFG1, CYREG_UDB_PA2_CFG1
.set SW__PA__CFG10, CYREG_UDB_PA2_CFG10
.set SW__PA__CFG11, CYREG_UDB_PA2_CFG11
.set SW__PA__CFG12, CYREG_UDB_PA2_CFG12
.set SW__PA__CFG13, CYREG_UDB_PA2_CFG13
.set SW__PA__CFG14, CYREG_UDB_PA2_CFG14
.set SW__PA__CFG2, CYREG_UDB_PA2_CFG2
.set SW__PA__CFG3, CYREG_UDB_PA2_CFG3
.set SW__PA__CFG4, CYREG_UDB_PA2_CFG4
.set SW__PA__CFG5, CYREG_UDB_PA2_CFG5
.set SW__PA__CFG6, CYREG_UDB_PA2_CFG6
.set SW__PA__CFG7, CYREG_UDB_PA2_CFG7
.set SW__PA__CFG8, CYREG_UDB_PA2_CFG8
.set SW__PA__CFG9, CYREG_UDB_PA2_CFG9
.set SW__PC, CYREG_GPIO_PRT2_PC
.set SW__PC2, CYREG_GPIO_PRT2_PC2
.set SW__PORT, 2
.set SW__PS, CYREG_GPIO_PRT2_PS
.set SW__SHIFT, 7

/* SwClk */
.set SwClk__CTRL_REGISTER, CYREG_PERI_PCLK_CTL11
.set SwClk__DIV_ID, 0x00000042
.set SwClk__DIV_REGISTER, CYREG_PERI_DIV_16_CTL2
.set SwClk__PA_DIV_ID, 0x000000FF

/* TC_ISR */
.set TC_ISR__INTC_CLR_EN_REG, CYREG_CM0_ICER
.set TC_ISR__INTC_CLR_PD_REG, CYREG_CM0_ICPR
.set TC_ISR__INTC_MASK, 0x100000
.set TC_ISR__INTC_NUMBER, 20
.set TC_ISR__INTC_PRIOR_MASK, 0xC0
.set TC_ISR__INTC_PRIOR_NUM, 3
.set TC_ISR__INTC_PRIOR_REG, CYREG_CM0_IPR5
.set TC_ISR__INTC_SET_EN_REG, CYREG_CM0_ISER
.set TC_ISR__INTC_SET_PD_REG, CYREG_CM0_ISPR
.set TC_ISR_1__INTC_CLR_EN_REG, CYREG_CM0_ICER
.set TC_ISR_1__INTC_CLR_PD_REG, CYREG_CM0_ICPR
.set TC_ISR_1__INTC_MASK, 0x20000
.set TC_ISR_1__INTC_NUMBER, 17
.set TC_ISR_1__INTC_PRIOR_MASK, 0xC000
.set TC_ISR_1__INTC_PRIOR_NUM, 3
.set TC_ISR_1__INTC_PRIOR_REG, CYREG_CM0_IPR4
.set TC_ISR_1__INTC_SET_EN_REG, CYREG_CM0_ISER
.set TC_ISR_1__INTC_SET_PD_REG, CYREG_CM0_ISPR

/* Timer_1_TimerUDB */
.set Timer_1_TimerUDB_rstSts_stsreg__0__MASK, 0x01
.set Timer_1_TimerUDB_rstSts_stsreg__0__POS, 0
.set Timer_1_TimerUDB_rstSts_stsreg__2__MASK, 0x04
.set Timer_1_TimerUDB_rstSts_stsreg__2__POS, 2
.set Timer_1_TimerUDB_rstSts_stsreg__3__MASK, 0x08
.set Timer_1_TimerUDB_rstSts_stsreg__3__POS, 3
.set Timer_1_TimerUDB_rstSts_stsreg__MASK, 0x0D
.set Timer_1_TimerUDB_rstSts_stsreg__MASK_REG, CYREG_UDB_W8_MSK3
.set Timer_1_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG, CYREG_UDB_W8_ACTL3
.set Timer_1_TimerUDB_rstSts_stsreg__STATUS_REG, CYREG_UDB_W8_ST3
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG, CYREG_UDB_W16_ACTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG, CYREG_UDB_W16_CTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG, CYREG_UDB_W16_CTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG, CYREG_UDB_W16_CTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG, CYREG_UDB_W16_CTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_MASK_REG, CYREG_UDB_W16_MSK0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG, CYREG_UDB_W16_MSK0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG, CYREG_UDB_W16_MSK0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG, CYREG_UDB_W16_MSK0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_CONTROL_AUX_CTL_REG, CYREG_UDB_W32_ACTL
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_CONTROL_REG, CYREG_UDB_W32_CTL
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_COUNT_REG, CYREG_UDB_W32_CTL
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_PERIOD_REG, CYREG_UDB_W32_MSK
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__MASK, 0x80
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__POS, 7
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_AUX_CTL_REG, CYREG_UDB_W8_ACTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG, CYREG_UDB_W8_CTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_ST_REG, CYREG_UDB_CAT16_CTL_ST0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_REG, CYREG_UDB_W8_CTL0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_ST_REG, CYREG_UDB_CAT16_CTL_ST0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK, 0x80
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK0
.set Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PERIOD_REG, CYREG_UDB_W8_MSK0
.set Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_A0_REG, CYREG_UDB_W16_A00
.set Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_A1_REG, CYREG_UDB_W16_A10
.set Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_D0_REG, CYREG_UDB_W16_D00
.set Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_D1_REG, CYREG_UDB_W16_D10
.set Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_DP_AUX_CTL_REG, CYREG_UDB_W16_ACTL0
.set Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_F0_REG, CYREG_UDB_W16_F00
.set Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_F1_REG, CYREG_UDB_W16_F10
.set Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_A0_REG, CYREG_UDB_W32_A0
.set Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_A1_REG, CYREG_UDB_W32_A1
.set Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_D0_REG, CYREG_UDB_W32_D0
.set Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_D1_REG, CYREG_UDB_W32_D1
.set Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_DP_AUX_CTL_REG, CYREG_UDB_W32_ACTL
.set Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_F0_REG, CYREG_UDB_W32_F0
.set Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_F1_REG, CYREG_UDB_W32_F1
.set Timer_1_TimerUDB_sT32_timerdp_u0__A0_A1_REG, CYREG_UDB_CAT16_A0
.set Timer_1_TimerUDB_sT32_timerdp_u0__A0_REG, CYREG_UDB_W8_A00
.set Timer_1_TimerUDB_sT32_timerdp_u0__A1_REG, CYREG_UDB_W8_A10
.set Timer_1_TimerUDB_sT32_timerdp_u0__D0_D1_REG, CYREG_UDB_CAT16_D0
.set Timer_1_TimerUDB_sT32_timerdp_u0__D0_REG, CYREG_UDB_W8_D00
.set Timer_1_TimerUDB_sT32_timerdp_u0__D1_REG, CYREG_UDB_W8_D10
.set Timer_1_TimerUDB_sT32_timerdp_u0__DP_AUX_CTL_REG, CYREG_UDB_W8_ACTL0
.set Timer_1_TimerUDB_sT32_timerdp_u0__F0_F1_REG, CYREG_UDB_CAT16_F0
.set Timer_1_TimerUDB_sT32_timerdp_u0__F0_REG, CYREG_UDB_W8_F00
.set Timer_1_TimerUDB_sT32_timerdp_u0__F1_REG, CYREG_UDB_W8_F10
.set Timer_1_TimerUDB_sT32_timerdp_u0__MSK_DP_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK0
.set Timer_1_TimerUDB_sT32_timerdp_u0__PER_DP_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK0
.set Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_A0_REG, CYREG_UDB_W16_A01
.set Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_A1_REG, CYREG_UDB_W16_A11
.set Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_D0_REG, CYREG_UDB_W16_D01
.set Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_D1_REG, CYREG_UDB_W16_D11
.set Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_DP_AUX_CTL_REG, CYREG_UDB_W16_ACTL1
.set Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_F0_REG, CYREG_UDB_W16_F01
.set Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_F1_REG, CYREG_UDB_W16_F11
.set Timer_1_TimerUDB_sT32_timerdp_u1__A0_A1_REG, CYREG_UDB_CAT16_A1
.set Timer_1_TimerUDB_sT32_timerdp_u1__A0_REG, CYREG_UDB_W8_A01
.set Timer_1_TimerUDB_sT32_timerdp_u1__A1_REG, CYREG_UDB_W8_A11
.set Timer_1_TimerUDB_sT32_timerdp_u1__D0_D1_REG, CYREG_UDB_CAT16_D1
.set Timer_1_TimerUDB_sT32_timerdp_u1__D0_REG, CYREG_UDB_W8_D01
.set Timer_1_TimerUDB_sT32_timerdp_u1__D1_REG, CYREG_UDB_W8_D11
.set Timer_1_TimerUDB_sT32_timerdp_u1__DP_AUX_CTL_REG, CYREG_UDB_W8_ACTL1
.set Timer_1_TimerUDB_sT32_timerdp_u1__F0_F1_REG, CYREG_UDB_CAT16_F1
.set Timer_1_TimerUDB_sT32_timerdp_u1__F0_REG, CYREG_UDB_W8_F01
.set Timer_1_TimerUDB_sT32_timerdp_u1__F1_REG, CYREG_UDB_W8_F11
.set Timer_1_TimerUDB_sT32_timerdp_u1__MSK_DP_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK1
.set Timer_1_TimerUDB_sT32_timerdp_u1__PER_DP_AUX_CTL_REG, CYREG_UDB_CAT16_ACTL_MSK1
.set Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_A0_REG, CYREG_UDB_W16_A02
.set Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_A1_REG, CYREG_UDB_W16_A12
.set Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_D0_REG, CYREG_UDB_W16_D02
.set Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_D1_REG, CYREG_UDB_W16_D12
.set Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_DP_AUX_CTL_REG, CYREG_UDB_W16_ACTL2
.set Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_F0_REG, CYREG_UDB_W16_F02
.set Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_F1_REG, CYREG_UDB_W16_F12
.set Timer_1_TimerUDB_sT32_timerdp_u2__A0_A1_REG, CYREG_UDB_CAT16_A2
.set Timer_1_TimerUDB_sT32_timerdp_u2__A0_REG, CYREG_UDB_W8_A02
.set Timer_1_TimerUDB_sT32_timerdp_u2__A1_REG, CYREG_UDB_W8_A12
.set Timer_1_TimerUDB_sT32_timerdp_u2__D0_D1_REG, CYREG_UDB_CAT16_D2
.set Timer_1_TimerUDB_sT32_timerdp_u2__D0_REG, CYREG_UDB_W8_D02
.set Timer_1_TimerUDB_sT32_timerdp_u2__D1_REG, CYREG_UDB_W8_D12
.set Timer_1_TimerUDB_sT32_timerdp_u2__DP_AUX_CTL_REG, CYREG_UDB_W8_ACTL2
.set Timer_1_TimerUDB_sT32_timerdp_u2__F0_F1_REG, CYREG_UDB_CAT16_F2
.set Timer_1_TimerUDB_sT32_timerdp_u2__F0_REG, CYREG_UDB_W8_F02
.set Timer_1_TimerUDB_sT32_timerdp_u2__F1_REG, CYREG_UDB_W8_F12
.set Timer_1_TimerUDB_sT32_timerdp_u3__A0_A1_REG, CYREG_UDB_CAT16_A3
.set Timer_1_TimerUDB_sT32_timerdp_u3__A0_REG, CYREG_UDB_W8_A03
.set Timer_1_TimerUDB_sT32_timerdp_u3__A1_REG, CYREG_UDB_W8_A13
.set Timer_1_TimerUDB_sT32_timerdp_u3__D0_D1_REG, CYREG_UDB_CAT16_D3
.set Timer_1_TimerUDB_sT32_timerdp_u3__D0_REG, CYREG_UDB_W8_D03
.set Timer_1_TimerUDB_sT32_timerdp_u3__D1_REG, CYREG_UDB_W8_D13
.set Timer_1_TimerUDB_sT32_timerdp_u3__DP_AUX_CTL_REG, CYREG_UDB_W8_ACTL3
.set Timer_1_TimerUDB_sT32_timerdp_u3__F0_F1_REG, CYREG_UDB_CAT16_F3
.set Timer_1_TimerUDB_sT32_timerdp_u3__F0_REG, CYREG_UDB_W8_F03
.set Timer_1_TimerUDB_sT32_timerdp_u3__F1_REG, CYREG_UDB_W8_F13

/* UART */
.set UART_rx__0__DR, CYREG_GPIO_PRT1_DR
.set UART_rx__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set UART_rx__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set UART_rx__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set UART_rx__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set UART_rx__0__HSIOM_GPIO, 0
.set UART_rx__0__HSIOM_I2C, 14
.set UART_rx__0__HSIOM_I2C_SDA, 14
.set UART_rx__0__HSIOM_MASK, 0x000F0000
.set UART_rx__0__HSIOM_SHIFT, 16
.set UART_rx__0__HSIOM_SPI, 15
.set UART_rx__0__HSIOM_SPI_MOSI, 15
.set UART_rx__0__HSIOM_UART, 9
.set UART_rx__0__HSIOM_UART_RX, 9
.set UART_rx__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_rx__0__INTR, CYREG_GPIO_PRT1_INTR
.set UART_rx__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_rx__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set UART_rx__0__MASK, 0x10
.set UART_rx__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set UART_rx__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set UART_rx__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set UART_rx__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set UART_rx__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set UART_rx__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set UART_rx__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set UART_rx__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set UART_rx__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set UART_rx__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set UART_rx__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set UART_rx__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set UART_rx__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set UART_rx__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set UART_rx__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set UART_rx__0__PC, CYREG_GPIO_PRT1_PC
.set UART_rx__0__PC2, CYREG_GPIO_PRT1_PC2
.set UART_rx__0__PORT, 1
.set UART_rx__0__PS, CYREG_GPIO_PRT1_PS
.set UART_rx__0__SHIFT, 4
.set UART_rx__DR, CYREG_GPIO_PRT1_DR
.set UART_rx__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set UART_rx__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set UART_rx__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set UART_rx__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_rx__INTR, CYREG_GPIO_PRT1_INTR
.set UART_rx__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_rx__INTSTAT, CYREG_GPIO_PRT1_INTR
.set UART_rx__MASK, 0x10
.set UART_rx__PA__CFG0, CYREG_UDB_PA1_CFG0
.set UART_rx__PA__CFG1, CYREG_UDB_PA1_CFG1
.set UART_rx__PA__CFG10, CYREG_UDB_PA1_CFG10
.set UART_rx__PA__CFG11, CYREG_UDB_PA1_CFG11
.set UART_rx__PA__CFG12, CYREG_UDB_PA1_CFG12
.set UART_rx__PA__CFG13, CYREG_UDB_PA1_CFG13
.set UART_rx__PA__CFG14, CYREG_UDB_PA1_CFG14
.set UART_rx__PA__CFG2, CYREG_UDB_PA1_CFG2
.set UART_rx__PA__CFG3, CYREG_UDB_PA1_CFG3
.set UART_rx__PA__CFG4, CYREG_UDB_PA1_CFG4
.set UART_rx__PA__CFG5, CYREG_UDB_PA1_CFG5
.set UART_rx__PA__CFG6, CYREG_UDB_PA1_CFG6
.set UART_rx__PA__CFG7, CYREG_UDB_PA1_CFG7
.set UART_rx__PA__CFG8, CYREG_UDB_PA1_CFG8
.set UART_rx__PA__CFG9, CYREG_UDB_PA1_CFG9
.set UART_rx__PC, CYREG_GPIO_PRT1_PC
.set UART_rx__PC2, CYREG_GPIO_PRT1_PC2
.set UART_rx__PORT, 1
.set UART_rx__PS, CYREG_GPIO_PRT1_PS
.set UART_rx__SHIFT, 4
.set UART_SCB__CTRL, CYREG_SCB0_CTRL
.set UART_SCB__EZ_DATA0, CYREG_SCB0_EZ_DATA0
.set UART_SCB__EZ_DATA1, CYREG_SCB0_EZ_DATA1
.set UART_SCB__EZ_DATA10, CYREG_SCB0_EZ_DATA10
.set UART_SCB__EZ_DATA11, CYREG_SCB0_EZ_DATA11
.set UART_SCB__EZ_DATA12, CYREG_SCB0_EZ_DATA12
.set UART_SCB__EZ_DATA13, CYREG_SCB0_EZ_DATA13
.set UART_SCB__EZ_DATA14, CYREG_SCB0_EZ_DATA14
.set UART_SCB__EZ_DATA15, CYREG_SCB0_EZ_DATA15
.set UART_SCB__EZ_DATA16, CYREG_SCB0_EZ_DATA16
.set UART_SCB__EZ_DATA17, CYREG_SCB0_EZ_DATA17
.set UART_SCB__EZ_DATA18, CYREG_SCB0_EZ_DATA18
.set UART_SCB__EZ_DATA19, CYREG_SCB0_EZ_DATA19
.set UART_SCB__EZ_DATA2, CYREG_SCB0_EZ_DATA2
.set UART_SCB__EZ_DATA20, CYREG_SCB0_EZ_DATA20
.set UART_SCB__EZ_DATA21, CYREG_SCB0_EZ_DATA21
.set UART_SCB__EZ_DATA22, CYREG_SCB0_EZ_DATA22
.set UART_SCB__EZ_DATA23, CYREG_SCB0_EZ_DATA23
.set UART_SCB__EZ_DATA24, CYREG_SCB0_EZ_DATA24
.set UART_SCB__EZ_DATA25, CYREG_SCB0_EZ_DATA25
.set UART_SCB__EZ_DATA26, CYREG_SCB0_EZ_DATA26
.set UART_SCB__EZ_DATA27, CYREG_SCB0_EZ_DATA27
.set UART_SCB__EZ_DATA28, CYREG_SCB0_EZ_DATA28
.set UART_SCB__EZ_DATA29, CYREG_SCB0_EZ_DATA29
.set UART_SCB__EZ_DATA3, CYREG_SCB0_EZ_DATA3
.set UART_SCB__EZ_DATA30, CYREG_SCB0_EZ_DATA30
.set UART_SCB__EZ_DATA31, CYREG_SCB0_EZ_DATA31
.set UART_SCB__EZ_DATA4, CYREG_SCB0_EZ_DATA4
.set UART_SCB__EZ_DATA5, CYREG_SCB0_EZ_DATA5
.set UART_SCB__EZ_DATA6, CYREG_SCB0_EZ_DATA6
.set UART_SCB__EZ_DATA7, CYREG_SCB0_EZ_DATA7
.set UART_SCB__EZ_DATA8, CYREG_SCB0_EZ_DATA8
.set UART_SCB__EZ_DATA9, CYREG_SCB0_EZ_DATA9
.set UART_SCB__I2C_CFG, CYREG_SCB0_I2C_CFG
.set UART_SCB__I2C_CTRL, CYREG_SCB0_I2C_CTRL
.set UART_SCB__I2C_M_CMD, CYREG_SCB0_I2C_M_CMD
.set UART_SCB__I2C_S_CMD, CYREG_SCB0_I2C_S_CMD
.set UART_SCB__I2C_STATUS, CYREG_SCB0_I2C_STATUS
.set UART_SCB__INTR_CAUSE, CYREG_SCB0_INTR_CAUSE
.set UART_SCB__INTR_I2C_EC, CYREG_SCB0_INTR_I2C_EC
.set UART_SCB__INTR_I2C_EC_MASK, CYREG_SCB0_INTR_I2C_EC_MASK
.set UART_SCB__INTR_I2C_EC_MASKED, CYREG_SCB0_INTR_I2C_EC_MASKED
.set UART_SCB__INTR_M, CYREG_SCB0_INTR_M
.set UART_SCB__INTR_M_MASK, CYREG_SCB0_INTR_M_MASK
.set UART_SCB__INTR_M_MASKED, CYREG_SCB0_INTR_M_MASKED
.set UART_SCB__INTR_M_SET, CYREG_SCB0_INTR_M_SET
.set UART_SCB__INTR_RX, CYREG_SCB0_INTR_RX
.set UART_SCB__INTR_RX_MASK, CYREG_SCB0_INTR_RX_MASK
.set UART_SCB__INTR_RX_MASKED, CYREG_SCB0_INTR_RX_MASKED
.set UART_SCB__INTR_RX_SET, CYREG_SCB0_INTR_RX_SET
.set UART_SCB__INTR_S, CYREG_SCB0_INTR_S
.set UART_SCB__INTR_S_MASK, CYREG_SCB0_INTR_S_MASK
.set UART_SCB__INTR_S_MASKED, CYREG_SCB0_INTR_S_MASKED
.set UART_SCB__INTR_S_SET, CYREG_SCB0_INTR_S_SET
.set UART_SCB__INTR_SPI_EC, CYREG_SCB0_INTR_SPI_EC
.set UART_SCB__INTR_SPI_EC_MASK, CYREG_SCB0_INTR_SPI_EC_MASK
.set UART_SCB__INTR_SPI_EC_MASKED, CYREG_SCB0_INTR_SPI_EC_MASKED
.set UART_SCB__INTR_TX, CYREG_SCB0_INTR_TX
.set UART_SCB__INTR_TX_MASK, CYREG_SCB0_INTR_TX_MASK
.set UART_SCB__INTR_TX_MASKED, CYREG_SCB0_INTR_TX_MASKED
.set UART_SCB__INTR_TX_SET, CYREG_SCB0_INTR_TX_SET
.set UART_SCB__RX_CTRL, CYREG_SCB0_RX_CTRL
.set UART_SCB__RX_FIFO_CTRL, CYREG_SCB0_RX_FIFO_CTRL
.set UART_SCB__RX_FIFO_RD, CYREG_SCB0_RX_FIFO_RD
.set UART_SCB__RX_FIFO_RD_SILENT, CYREG_SCB0_RX_FIFO_RD_SILENT
.set UART_SCB__RX_FIFO_STATUS, CYREG_SCB0_RX_FIFO_STATUS
.set UART_SCB__RX_MATCH, CYREG_SCB0_RX_MATCH
.set UART_SCB__SPI_CTRL, CYREG_SCB0_SPI_CTRL
.set UART_SCB__SPI_STATUS, CYREG_SCB0_SPI_STATUS
.set UART_SCB__SS0_POSISTION, 0
.set UART_SCB__SS1_POSISTION, 1
.set UART_SCB__SS2_POSISTION, 2
.set UART_SCB__SS3_POSISTION, 3
.set UART_SCB__STATUS, CYREG_SCB0_STATUS
.set UART_SCB__TX_CTRL, CYREG_SCB0_TX_CTRL
.set UART_SCB__TX_FIFO_CTRL, CYREG_SCB0_TX_FIFO_CTRL
.set UART_SCB__TX_FIFO_STATUS, CYREG_SCB0_TX_FIFO_STATUS
.set UART_SCB__TX_FIFO_WR, CYREG_SCB0_TX_FIFO_WR
.set UART_SCB__UART_CTRL, CYREG_SCB0_UART_CTRL
.set UART_SCB__UART_FLOW_CTRL, CYREG_SCB0_UART_FLOW_CTRL
.set UART_SCB__UART_RX_CTRL, CYREG_SCB0_UART_RX_CTRL
.set UART_SCB__UART_RX_STATUS, CYREG_SCB0_UART_RX_STATUS
.set UART_SCB__UART_TX_CTRL, CYREG_SCB0_UART_TX_CTRL
.set UART_SCBCLK__CTRL_REGISTER, CYREG_PERI_PCLK_CTL1
.set UART_SCBCLK__DIV_ID, 0x00000040
.set UART_SCBCLK__DIV_REGISTER, CYREG_PERI_DIV_16_CTL0
.set UART_SCBCLK__PA_DIV_ID, 0x000000FF
.set UART_tx__0__DR, CYREG_GPIO_PRT1_DR
.set UART_tx__0__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set UART_tx__0__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set UART_tx__0__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set UART_tx__0__HSIOM, CYREG_HSIOM_PORT_SEL1
.set UART_tx__0__HSIOM_GPIO, 0
.set UART_tx__0__HSIOM_I2C, 14
.set UART_tx__0__HSIOM_I2C_SCL, 14
.set UART_tx__0__HSIOM_MASK, 0x00F00000
.set UART_tx__0__HSIOM_SHIFT, 20
.set UART_tx__0__HSIOM_SPI, 15
.set UART_tx__0__HSIOM_SPI_MISO, 15
.set UART_tx__0__HSIOM_UART, 9
.set UART_tx__0__HSIOM_UART_TX, 9
.set UART_tx__0__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_tx__0__INTR, CYREG_GPIO_PRT1_INTR
.set UART_tx__0__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_tx__0__INTSTAT, CYREG_GPIO_PRT1_INTR
.set UART_tx__0__MASK, 0x20
.set UART_tx__0__OUT_SEL, CYREG_UDB_PA1_CFG10
.set UART_tx__0__OUT_SEL_SHIFT, 10
.set UART_tx__0__OUT_SEL_VAL, -1
.set UART_tx__0__PA__CFG0, CYREG_UDB_PA1_CFG0
.set UART_tx__0__PA__CFG1, CYREG_UDB_PA1_CFG1
.set UART_tx__0__PA__CFG10, CYREG_UDB_PA1_CFG10
.set UART_tx__0__PA__CFG11, CYREG_UDB_PA1_CFG11
.set UART_tx__0__PA__CFG12, CYREG_UDB_PA1_CFG12
.set UART_tx__0__PA__CFG13, CYREG_UDB_PA1_CFG13
.set UART_tx__0__PA__CFG14, CYREG_UDB_PA1_CFG14
.set UART_tx__0__PA__CFG2, CYREG_UDB_PA1_CFG2
.set UART_tx__0__PA__CFG3, CYREG_UDB_PA1_CFG3
.set UART_tx__0__PA__CFG4, CYREG_UDB_PA1_CFG4
.set UART_tx__0__PA__CFG5, CYREG_UDB_PA1_CFG5
.set UART_tx__0__PA__CFG6, CYREG_UDB_PA1_CFG6
.set UART_tx__0__PA__CFG7, CYREG_UDB_PA1_CFG7
.set UART_tx__0__PA__CFG8, CYREG_UDB_PA1_CFG8
.set UART_tx__0__PA__CFG9, CYREG_UDB_PA1_CFG9
.set UART_tx__0__PC, CYREG_GPIO_PRT1_PC
.set UART_tx__0__PC2, CYREG_GPIO_PRT1_PC2
.set UART_tx__0__PORT, 1
.set UART_tx__0__PS, CYREG_GPIO_PRT1_PS
.set UART_tx__0__SHIFT, 5
.set UART_tx__DR, CYREG_GPIO_PRT1_DR
.set UART_tx__DR_CLR, CYREG_GPIO_PRT1_DR_CLR
.set UART_tx__DR_INV, CYREG_GPIO_PRT1_DR_INV
.set UART_tx__DR_SET, CYREG_GPIO_PRT1_DR_SET
.set UART_tx__INTCFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_tx__INTR, CYREG_GPIO_PRT1_INTR
.set UART_tx__INTR_CFG, CYREG_GPIO_PRT1_INTR_CFG
.set UART_tx__INTSTAT, CYREG_GPIO_PRT1_INTR
.set UART_tx__MASK, 0x20
.set UART_tx__PA__CFG0, CYREG_UDB_PA1_CFG0
.set UART_tx__PA__CFG1, CYREG_UDB_PA1_CFG1
.set UART_tx__PA__CFG10, CYREG_UDB_PA1_CFG10
.set UART_tx__PA__CFG11, CYREG_UDB_PA1_CFG11
.set UART_tx__PA__CFG12, CYREG_UDB_PA1_CFG12
.set UART_tx__PA__CFG13, CYREG_UDB_PA1_CFG13
.set UART_tx__PA__CFG14, CYREG_UDB_PA1_CFG14
.set UART_tx__PA__CFG2, CYREG_UDB_PA1_CFG2
.set UART_tx__PA__CFG3, CYREG_UDB_PA1_CFG3
.set UART_tx__PA__CFG4, CYREG_UDB_PA1_CFG4
.set UART_tx__PA__CFG5, CYREG_UDB_PA1_CFG5
.set UART_tx__PA__CFG6, CYREG_UDB_PA1_CFG6
.set UART_tx__PA__CFG7, CYREG_UDB_PA1_CFG7
.set UART_tx__PA__CFG8, CYREG_UDB_PA1_CFG8
.set UART_tx__PA__CFG9, CYREG_UDB_PA1_CFG9
.set UART_tx__PC, CYREG_GPIO_PRT1_PC
.set UART_tx__PC2, CYREG_GPIO_PRT1_PC2
.set UART_tx__PORT, 1
.set UART_tx__PS, CYREG_GPIO_PRT1_PS
.set UART_tx__SHIFT, 5

/* isr_1 */
.set isr_1__INTC_CLR_EN_REG, CYREG_CM0_ICER
.set isr_1__INTC_CLR_PD_REG, CYREG_CM0_ICPR
.set isr_1__INTC_MASK, 0x04
.set isr_1__INTC_NUMBER, 2
.set isr_1__INTC_PRIOR_MASK, 0xC00000
.set isr_1__INTC_PRIOR_NUM, 3
.set isr_1__INTC_PRIOR_REG, CYREG_CM0_IPR0
.set isr_1__INTC_SET_EN_REG, CYREG_CM0_ISER
.set isr_1__INTC_SET_PD_REG, CYREG_CM0_ISPR

/* Miscellaneous */
.set CYDEV_BCLK__HFCLK__HZ, 24000000
.set CYDEV_BCLK__HFCLK__KHZ, 24000
.set CYDEV_BCLK__HFCLK__MHZ, 24
.set CYDEV_BCLK__SYSCLK__HZ, 24000000
.set CYDEV_BCLK__SYSCLK__KHZ, 24000
.set CYDEV_BCLK__SYSCLK__MHZ, 24
.set CYDEV_CHIP_DIE_LEOPARD, 1
.set CYDEV_CHIP_DIE_PSOC4A, 16
.set CYDEV_CHIP_DIE_PSOC5LP, 2
.set CYDEV_CHIP_DIE_PSOC5TM, 3
.set CYDEV_CHIP_DIE_TMA4, 4
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_FM0P, 5
.set CYDEV_CHIP_FAMILY_FM3, 6
.set CYDEV_CHIP_FAMILY_FM4, 7
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_FAMILY_PSOC6, 4
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC4
.set CYDEV_CHIP_JTAG_ID, 0x0E34119E
.set CYDEV_CHIP_MEMBER_3A, 1
.set CYDEV_CHIP_MEMBER_4A, 16
.set CYDEV_CHIP_MEMBER_4D, 12
.set CYDEV_CHIP_MEMBER_4E, 6
.set CYDEV_CHIP_MEMBER_4F, 17
.set CYDEV_CHIP_MEMBER_4G, 4
.set CYDEV_CHIP_MEMBER_4H, 15
.set CYDEV_CHIP_MEMBER_4I, 21
.set CYDEV_CHIP_MEMBER_4J, 13
.set CYDEV_CHIP_MEMBER_4K, 14
.set CYDEV_CHIP_MEMBER_4L, 20
.set CYDEV_CHIP_MEMBER_4M, 19
.set CYDEV_CHIP_MEMBER_4N, 9
.set CYDEV_CHIP_MEMBER_4O, 7
.set CYDEV_CHIP_MEMBER_4P, 18
.set CYDEV_CHIP_MEMBER_4Q, 11
.set CYDEV_CHIP_MEMBER_4R, 8
.set CYDEV_CHIP_MEMBER_4S, 10
.set CYDEV_CHIP_MEMBER_4U, 5
.set CYDEV_CHIP_MEMBER_5A, 3
.set CYDEV_CHIP_MEMBER_5B, 2
.set CYDEV_CHIP_MEMBER_6A, 22
.set CYDEV_CHIP_MEMBER_FM3, 26
.set CYDEV_CHIP_MEMBER_FM4, 27
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24
.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_4F
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0
.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1
.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1
.set CYDEV_CHIP_REV_TMA4_ES, 17
.set CYDEV_CHIP_REV_TMA4_ES2, 33
.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
.set CYDEV_CHIP_REVISION_4G_ES, 17
.set CYDEV_CHIP_REVISION_4G_ES2, 33
.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CHIP_REVISION_5B_ES0, 0
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0
.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_4F_PRODUCTION
.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
.set CYDEV_CONFIG_READ_ACCELERATOR, 1
.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_Disallowed
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_CONFIGURATION_MODE_DMA, 2
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
.set CYDEV_DEBUG_PROTECT_KILL, 4
.set CYDEV_DEBUG_PROTECT_OPEN, 1
.set CYDEV_DEBUG_PROTECT, CYDEV_DEBUG_PROTECT_OPEN
.set CYDEV_DEBUG_PROTECT_PROTECTED, 2
.set CYDEV_DEBUGGING_DPS_Disable, 3
.set CYDEV_DEBUGGING_DPS_SWD, 2
.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD
.set CYDEV_DEBUGGING_ENABLE, 1
.set CYDEV_DFT_SELECT_CLK0, 10
.set CYDEV_DFT_SELECT_CLK1, 11
.set CYDEV_HEAP_SIZE, 0x200
.set CYDEV_IMO_TRIMMED_BY_USB, 0
.set CYDEV_IMO_TRIMMED_BY_WCO, 0
.set CYDEV_IS_EXPORTING_CODE, 0
.set CYDEV_IS_IMPORTING_CODE, 0
.set CYDEV_PROJ_TYPE, 0
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LAUNCHER, 5
.set CYDEV_PROJ_TYPE_LOADABLE, 2
.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_STACK_SIZE, 0x0800
.set CYDEV_USE_BUNDLED_CMSIS, 1
.set CYDEV_VARIABLE_VDDA, 1
.set CYDEV_VDDA_MV, 3300
.set CYDEV_VDDD_MV, 3300
.set CYDEV_VDDR_MV, 3300
.set CYDEV_WDT_GENERATE_ISR, 1
.set CYIPBLOCK_m0s8bless_VERSION, 1
.set CYIPBLOCK_m0s8cpussv2_VERSION, 1
.set CYIPBLOCK_m0s8csd_VERSION, 1
.set CYIPBLOCK_m0s8ioss_VERSION, 1
.set CYIPBLOCK_m0s8lcd_VERSION, 2
.set CYIPBLOCK_m0s8lpcomp_VERSION, 2
.set CYIPBLOCK_m0s8peri_VERSION, 1
.set CYIPBLOCK_m0s8scb_VERSION, 2
.set CYIPBLOCK_m0s8srssv2_VERSION, 1
.set CYIPBLOCK_m0s8tcpwm_VERSION, 2
.set CYIPBLOCK_m0s8udbif_VERSION, 1
.set CYIPBLOCK_s8pass4al_VERSION, 1
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif
