Static Timing Analysis

Project : UDB_buffer_t_pointer
Build Time : 01/04/18 02:08:25
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
SPI_IntClock CyMASTER_CLK 2.000 MHz 2.000 MHz 72.780 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:sR8:Dp:u0\/f1_load 72.780 MHz 13.740 486.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPI:BSPIM:count_0\ \SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:load_rx_data\/main_4 2.963
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_4 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:sR8:Dp:u0\/f1_load 73.573 MHz 13.592 486.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_rx_data\/main_1 2.815
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_1 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:sR8:Dp:u0\/f1_load 73.681 MHz 13.572 486.428
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPI:BSPIM:count_1\ \SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:load_rx_data\/main_3 2.795
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_3 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:sR8:Dp:u0\/f1_load 74.566 MHz 13.411 486.589
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:load_rx_data\/main_0 2.634
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_0 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:sR8:Dp:u0\/f1_load 74.671 MHz 13.392 486.608
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:load_rx_data\/main_2 2.615
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_2 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:sR8:Dp:u0\/f1_load 2.637
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPI:BSPIM:RxStsReg\/status_6 78.094 MHz 12.805 487.195
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR8:Dp:u0\ \SPI:BSPIM:sR8:Dp:u0\/clock \SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \SPI:BSPIM:rx_status_4\ \SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPI:BSPIM:rx_status_6\/main_5 3.050
macrocell4 U(3,2) 1 \SPI:BSPIM:rx_status_6\ \SPI:BSPIM:rx_status_6\/main_5 \SPI:BSPIM:rx_status_6\/q 3.350
Route 1 \SPI:BSPIM:rx_status_6\ \SPI:BSPIM:rx_status_6\/q \SPI:BSPIM:RxStsReg\/status_6 2.325
statusicell2 U(2,2) 1 \SPI:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:TxStsReg\/status_3 82.136 MHz 12.175 487.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPI:BSPIM:count_0\ \SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:load_rx_data\/main_4 2.963
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_4 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:TxStsReg\/status_3 3.422
statusicell1 U(3,2) 1 \SPI:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:TxStsReg\/status_3 83.146 MHz 12.027 487.973
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_rx_data\/main_1 2.815
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_1 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:TxStsReg\/status_3 3.422
statusicell1 U(3,2) 1 \SPI:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:TxStsReg\/status_3 83.285 MHz 12.007 487.993
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPI:BSPIM:count_1\ \SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:load_rx_data\/main_3 2.795
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_3 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:TxStsReg\/status_3 3.422
statusicell1 U(3,2) 1 \SPI:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:TxStsReg\/status_3 84.417 MHz 11.846 488.154
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:load_rx_data\/main_0 2.634
macrocell1 U(3,1) 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/main_0 \SPI:BSPIM:load_rx_data\/q 3.350
Route 1 \SPI:BSPIM:load_rx_data\ \SPI:BSPIM:load_rx_data\/q \SPI:BSPIM:TxStsReg\/status_3 3.422
statusicell1 U(3,2) 1 \SPI:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:state_2\/main_5 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:state_2\/main_5 2.607
macrocell7 U(3,1) 1 \SPI:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:state_1\/main_5 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:state_1\/main_5 2.607
macrocell8 U(3,1) 1 \SPI:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:ld_ident\/main_5 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:ld_ident\/main_5 2.607
macrocell12 U(3,1) 1 \SPI:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_2 Net_23/main_7 3.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 Net_23/main_7 2.615
macrocell6 U(3,1) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:state_2\/main_3 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:state_2\/main_3 2.619
macrocell7 U(3,1) 1 \SPI:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:state_1\/main_3 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:state_1\/main_3 2.619
macrocell8 U(3,1) 1 \SPI:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:ld_ident\/main_3 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:ld_ident\/main_3 2.619
macrocell12 U(3,1) 1 \SPI:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 Net_23/main_5 3.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 Net_23/main_5 2.634
macrocell6 U(3,1) 1 Net_23 HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:state_2\/main_4 3.401
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:state_2\/main_4 2.781
macrocell7 U(3,1) 1 \SPI:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:state_1\/main_4 3.401
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:state_1\/main_4 2.781
macrocell8 U(3,1) 1 \SPI:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPI_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \SPI:BSPIM:sR8:Dp:u0\/route_si 15.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell1 P12[0] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 6.830
Route 1 Net_19 MISO(0)/fb \SPI:BSPIM:sR8:Dp:u0\/route_si 5.244
datapathcell1 U(3,1) 1 \SPI:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPI_IntClock
Source Destination Delay (ns)
Net_11/q SS_HW(0)_PAD 26.331
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,2) 1 Net_11 Net_11/clock_0 Net_11/q 1.250
Route 1 Net_11 Net_11/q SS_HW(0)/pin_input 8.466
iocell7 P12[4] 1 SS_HW(0) SS_HW(0)/pin_input SS_HW(0)/pad_out 16.615
Route 1 SS_HW(0)_PAD SS_HW(0)/pad_out SS_HW(0)_PAD 0.000
Clock Clock path delay 0.000
Net_23/q MOSI(0)_PAD 23.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,1) 1 Net_23 Net_23/clock_0 Net_23/q 1.250
Route 1 Net_23 Net_23/q MOSI(0)/pin_input 6.472
iocell2 P12[1] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 15.933
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_25/q SCLK(0)_PAD 23.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,2) 1 Net_25 Net_25/clock_0 Net_25/q 1.250
Route 1 Net_25 Net_25/q SCLK(0)/pin_input 6.119
iocell3 P12[2] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 15.666
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000