Static Timing Analysis

Project : DMA2
Build Time : 01/09/18 10:08:58
Device : CY8C6347BZI-BLD53
Temperature : -40C
VBACKUP : 3.30
VDDA : 3.30
VDDA_CSD : 3.30
VDDD : 3.30
VDDIO_0 : 3.30
VDDIO_0_RCV : 3.30
VDDIO_1 : 3.30
VDDIO_A : 3.30
VDDQ : 3.30
VDDR_HVL_2 : 3.30
VDDR_HVL_3 : 3.30
VDD_NS : 3.30
Voltage : 3.3
vddd : 3.30
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyClk_Fast CyClk_Fast 100.000 MHz 100.000 MHz N/A
CyClk_HF0 CyClk_HF0 100.000 MHz 100.000 MHz N/A
CyClk_LF CyClk_LF 32.000 kHz 32.000 kHz N/A
CyClk_Peri CyClk_Peri 50.000 MHz 50.000 MHz N/A
CyClk_Slow CyClk_Peri 50.000 MHz 50.000 MHz N/A
CapSense_ModClk CyClk_Peri 196.078 kHz 196.078 kHz N/A
CyFLL CyFLL 100.000 MHz 100.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 8.000 MHz 8.000 MHz N/A
CyPeriClk_App CyPeriClk_App 50.000 MHz 50.000 MHz N/A
Clock_4M8_App CyPeriClk_App 5.000 MHz 5.000 MHz N/A
Clock_24_App CyPeriClk_App 25.000 MHz 25.000 MHz 77.018 MHz
Clock_480K_App CyPeriClk_App 47.985 kHz 47.985 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 40ns(25 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ChangeDetect:cydff_1_1\/q Net_267_5/main_1 77.018 MHz 12.984 27.016
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(1,3) 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/clock_0 \ChangeDetect:cydff_1_1\/q 0.390
Route 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/q Net_537_split/main_9 1.871
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_9 Net_537_split/q 1.210
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_267_5/main_1 5.501
macrocell22 U(1,4) 1 Net_267_5 SETUP 1.710
Clock Skew 0.000
\ChangeDetect:cydff_1_1\/q Net_259_4/main_2 77.256 MHz 12.944 27.056
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(1,3) 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/clock_0 \ChangeDetect:cydff_1_1\/q 0.390
Route 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/q Net_537_split/main_9 1.871
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_9 Net_537_split/q 1.210
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_259_4/main_2 5.871
macrocell7 U(1,0) 1 Net_259_4 SETUP 1.300
Clock Skew 0.000
\ChangeDetect:cydff_1_1\/q Net_259_0/main_2 77.918 MHz 12.834 27.166
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(1,3) 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/clock_0 \ChangeDetect:cydff_1_1\/q 0.390
Route 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/q Net_537_split/main_9 1.871
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_9 Net_537_split/q 1.210
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_259_0/main_2 5.871
macrocell11 U(1,0) 1 Net_259_0 SETUP 1.190
Clock Skew 0.000
\ChangeDetect:cydff_1_2\/q Net_267_5/main_1 78.204 MHz 12.787 27.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(1,3) 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/clock_0 \ChangeDetect:cydff_1_2\/q 0.330
Route 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/q Net_537_split/main_8 1.694
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_8 Net_537_split/q 1.250
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_267_5/main_1 5.501
macrocell22 U(1,4) 1 Net_267_5 SETUP 1.710
Clock Skew 0.000
\ChangeDetect:cydff_1_1\/q Net_267_2/main_1 78.345 MHz 12.764 27.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(1,3) 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/clock_0 \ChangeDetect:cydff_1_1\/q 0.390
Route 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/q Net_537_split/main_9 1.871
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_9 Net_537_split/q 1.210
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_267_2/main_1 5.501
macrocell25 U(1,4) 1 Net_267_2 SETUP 1.490
Clock Skew 0.000
\ChangeDetect:cydff_1_2\/q Net_259_4/main_2 78.450 MHz 12.747 27.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(1,3) 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/clock_0 \ChangeDetect:cydff_1_2\/q 0.330
Route 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/q Net_537_split/main_8 1.694
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_8 Net_537_split/q 1.250
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_259_4/main_2 5.871
macrocell7 U(1,0) 1 Net_259_4 SETUP 1.300
Clock Skew 0.000
\ChangeDetect:cydff_1_1\/q Net_267_3/main_1 78.530 MHz 12.734 27.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(1,3) 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/clock_0 \ChangeDetect:cydff_1_1\/q 0.390
Route 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/q Net_537_split/main_9 1.871
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_9 Net_537_split/q 1.210
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_267_3/main_1 5.501
macrocell24 U(1,4) 1 Net_267_3 SETUP 1.460
Clock Skew 0.000
\ChangeDetect:cydff_1_1\/q Net_267_7/main_1 78.653 MHz 12.714 27.286
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(1,3) 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/clock_0 \ChangeDetect:cydff_1_1\/q 0.390
Route 1 \ChangeDetect:cydff_1_1\ \ChangeDetect:cydff_1_1\/q Net_537_split/main_9 1.871
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_9 Net_537_split/q 1.210
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_267_7/main_1 5.501
macrocell20 U(1,4) 1 Net_267_7 SETUP 1.440
Clock Skew 0.000
\ChangeDetect:cydff_1_2\/q Net_259_0/main_2 79.133 MHz 12.637 27.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(1,3) 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/clock_0 \ChangeDetect:cydff_1_2\/q 0.330
Route 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/q Net_537_split/main_8 1.694
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_8 Net_537_split/q 1.250
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_259_0/main_2 5.871
macrocell11 U(1,0) 1 Net_259_0 SETUP 1.190
Clock Skew 0.000
\ChangeDetect:cydff_1_2\/q Net_267_2/main_1 79.573 MHz 12.567 27.433
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(1,3) 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/clock_0 \ChangeDetect:cydff_1_2\/q 0.330
Route 1 \ChangeDetect:cydff_1_2\ \ChangeDetect:cydff_1_2\/q Net_537_split/main_8 1.694
macrocell1 U(1,2) 1 Net_537_split Net_537_split/main_8 Net_537_split/q 1.250
Route 1 Net_537_split Net_537_split/q Net_537/main_8 1.182
macrocell3 U(0,2) 1 Net_537 Net_537/main_8 Net_537/q 1.120
Route 1 Net_537 Net_537/q Net_267_2/main_1 5.501
macrocell25 U(1,4) 1 Net_267_2 SETUP 1.490
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_271_3/q Net_271_3/main_0 1.297
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(1,1) 1 Net_271_3 Net_271_3/clock_0 Net_271_3/q 0.240
macrocell32 U(1,1) 1 Net_271_3 Net_271_3/q Net_271_3/main_0 1.057
macrocell32 U(1,1) 1 Net_271_3 HOLD 0.000
Clock Skew 0.000
Net_259_5/q Net_259_5/main_0 1.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_259_5 Net_259_5/clock_0 Net_259_5/q 0.310
macrocell6 U(1,0) 1 Net_259_5 Net_259_5/q Net_259_5/main_0 0.990
macrocell6 U(1,0) 1 Net_259_5 HOLD 0.000
Clock Skew 0.000
Net_267_6/q Net_267_6/main_0 1.359
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,3) 1 Net_267_6 Net_267_6/clock_0 Net_267_6/q 0.310
macrocell21 U(0,3) 1 Net_267_6 Net_267_6/q Net_267_6/main_0 1.049
macrocell21 U(0,3) 1 Net_267_6 HOLD 0.000
Clock Skew 0.000
Net_271_7/q Net_271_7/main_0 1.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(1,1) 1 Net_271_7 Net_271_7/clock_0 Net_271_7/q 0.290
macrocell28 U(1,1) 1 Net_271_7 Net_271_7/q Net_271_7/main_0 1.083
macrocell28 U(1,1) 1 Net_271_7 HOLD 0.000
Clock Skew 0.000
Net_271_2/q Net_271_2/main_0 1.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(1,1) 1 Net_271_2 Net_271_2/clock_0 Net_271_2/q 0.270
macrocell33 U(1,1) 1 Net_271_2 Net_271_2/q Net_271_2/main_0 1.120
macrocell33 U(1,1) 1 Net_271_2 HOLD 0.000
Clock Skew 0.000
Net_259_6/q Net_259_6/main_0 1.398
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,3) 1 Net_259_6 Net_259_6/clock_0 Net_259_6/q 0.240
macrocell5 U(1,3) 1 Net_259_6 Net_259_6/q Net_259_6/main_0 1.158
macrocell5 U(1,3) 1 Net_259_6 HOLD 0.000
Clock Skew 0.000
Net_259_1/q Net_259_1/main_0 1.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 Net_259_1 Net_259_1/clock_0 Net_259_1/q 0.300
macrocell10 U(1,0) 1 Net_259_1 Net_259_1/q Net_259_1/main_0 1.120
macrocell10 U(1,0) 1 Net_259_1 HOLD 0.000
Clock Skew 0.000
Net_271_6/q Net_271_6/main_0 1.429
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,1) 1 Net_271_6 Net_271_6/clock_0 Net_271_6/q 0.340
macrocell29 U(1,1) 1 Net_271_6 Net_271_6/q Net_271_6/main_0 1.089
macrocell29 U(1,1) 1 Net_271_6 HOLD 0.000
Clock Skew 0.000
Net_263_3/q Net_263_3/main_0 1.459
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,3) 1 Net_263_3 Net_263_3/clock_0 Net_263_3/q 0.340
macrocell16 U(1,3) 1 Net_263_3 Net_263_3/q Net_263_3/main_0 1.119
macrocell16 U(1,3) 1 Net_263_3 HOLD 0.000
Clock Skew 0.000
Net_263_1/q Net_263_1/main_0 1.459
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,1) 1 Net_263_1 Net_263_1/clock_0 Net_263_1/q 0.340
macrocell18 U(1,1) 1 Net_263_1 Net_263_1/q Net_263_1/main_0 1.119
macrocell18 U(1,1) 1 Net_263_1 HOLD 0.000
Clock Skew 0.000