Static Timing Analysis

Project : ADC_DMA_VDAC01
Build Time : 12/06/17 17:35:57
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
VDDA : 5.00
VDDD : 5.00
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VDDOPAMP : 5.00
VUSB : 5.00
Voltage : 5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_1_Ext_CP_Clk ADC_DelSig_1_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_Ext_CP_Clk(routed) ADC_DelSig_1_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_theACLK(fixed-function) ADC_DelSig_1_theACLK(fixed-function) 160.000 kHz 160.000 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 58.716 MHz
ADC_DelSig_1_theACLK CyMASTER_CLK 160.000 kHz 160.000 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
\ADC_DelSig_1:DSM\/dec_clock \ADC_DelSig_1:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
DMA_1/termout \Status_Reg_1:sts:sts_reg\/status_0 58.716 MHz 17.031 24.636
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqContainer=(0)][DrqId=(10)] 1 DMA_1 DMA_1/clock DMA_1/termout 9.000
Route 1 Net_28 DMA_1/termout \Status_Reg_1:sts:sts_reg\/status_0 6.461
statuscell1 U(1,3) 1 \Status_Reg_1:sts:sts_reg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
DMA_1/termout \Status_Reg_1:sts:sts_reg\/status_0 13.461
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqContainer=(0)][DrqId=(10)] 1 DMA_1 DMA_1/clock DMA_1/termout 9.000
Route 1 Net_28 DMA_1/termout \Status_Reg_1:sts:sts_reg\/status_0 6.461
statuscell1 U(1,3) 1 \Status_Reg_1:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000