\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
58.096 MHz |
17.213 |
524.454 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(0,0) |
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/clock_0 |
\UART:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/q |
\UART:BUART:counter_load_not\/main_0 |
4.196 |
macrocell2 |
U(0,0) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_0 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.227 |
datapathcell2 |
U(0,0) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
61.847 MHz |
16.169 |
525.498 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell7 |
U(1,0) |
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/clock_0 |
\UART:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/q |
\UART:BUART:counter_load_not\/main_1 |
3.152 |
macrocell2 |
U(0,0) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_1 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.227 |
datapathcell2 |
U(0,0) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_2\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
63.119 MHz |
15.843 |
525.824 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell8 |
U(0,0) |
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/clock_0 |
\UART:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/q |
\UART:BUART:counter_load_not\/main_3 |
2.826 |
macrocell2 |
U(0,0) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_3 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.227 |
datapathcell2 |
U(0,0) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
65.699 MHz |
15.221 |
526.446 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(0,0) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART:BUART:tx_bitclk_enable_pre\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:counter_load_not\/main_2 |
3.264 |
macrocell2 |
U(0,0) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_2 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
2.227 |
datapathcell2 |
U(0,0) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:sTX:TxSts\/status_0 |
74.444 MHz |
13.433 |
528.234 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell1 |
U(1,0) |
1 |
\UART:BUART:sTX:TxShifter:u0\ |
\UART:BUART:sTX:TxShifter:u0\/clock |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
3.580 |
Route |
|
1 |
\UART:BUART:tx_fifo_empty\ |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:tx_status_0\/main_3 |
3.755 |
macrocell3 |
U(1,0) |
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/main_3 |
\UART:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/q |
\UART:BUART:sTX:TxSts\/status_0 |
2.248 |
statusicell1 |
U(1,0) |
1 |
\UART:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:TxShifter:u0\/cs_addr_2 |
83.459 MHz |
11.982 |
529.685 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(0,0) |
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/clock_0 |
\UART:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:TxShifter:u0\/cs_addr_2 |
4.722 |
datapathcell1 |
U(1,0) |
1 |
\UART:BUART:sTX:TxShifter:u0\ |
|
SETUP |
6.010 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:TxSts\/status_0 |
89.678 MHz |
11.151 |
530.516 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell6 |
U(0,0) |
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/clock_0 |
\UART:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/q |
\UART:BUART:tx_status_0\/main_0 |
3.803 |
macrocell3 |
U(1,0) |
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/main_0 |
\UART:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/q |
\UART:BUART:sTX:TxSts\/status_0 |
2.248 |
statusicell1 |
U(1,0) |
1 |
\UART:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:tx_state_0\/main_3 |
92.208 MHz |
10.845 |
530.822 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell1 |
U(1,0) |
1 |
\UART:BUART:sTX:TxShifter:u0\ |
\UART:BUART:sTX:TxShifter:u0\/clock |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
3.580 |
Route |
|
1 |
\UART:BUART:tx_fifo_empty\ |
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb |
\UART:BUART:tx_state_0\/main_3 |
3.755 |
macrocell7 |
U(1,0) |
1 |
\UART:BUART:tx_state_0\ |
|
SETUP |
3.510 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:TxSts\/status_0 |
95.220 MHz |
10.502 |
531.165 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell7 |
U(1,0) |
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/clock_0 |
\UART:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/q |
\UART:BUART:tx_status_0\/main_1 |
3.154 |
macrocell3 |
U(1,0) |
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/main_1 |
\UART:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/q |
\UART:BUART:sTX:TxSts\/status_0 |
2.248 |
statusicell1 |
U(1,0) |
1 |
\UART:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:TxShifter:u0\/cs_addr_1 |
95.969 MHz |
10.420 |
531.247 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell7 |
U(1,0) |
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/clock_0 |
\UART:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:TxShifter:u0\/cs_addr_1 |
3.160 |
datapathcell1 |
U(1,0) |
1 |
\UART:BUART:sTX:TxShifter:u0\ |
|
SETUP |
6.010 |
Clock |
|
|
|
|
Skew |
0.000 |
|