Static Timing Analysis

Project : Gen2
Build Time : 09/05/17 07:27:38
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 122.085 MHz
UDBClock CyHFCLK 24.000 MHz 24.000 MHz 40.746 MHz
NeoClock CyHFCLK 4.800 MHz 4.800 MHz 122.085 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_255/q Net_277/main_0 122.085 MHz 8.191 12.642
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 Net_255 Net_255/clock_0 Net_255/q 1.250
Route 1 Net_255 Net_255/q Net_277/main_0 3.431
macrocell7 U(1,0) 1 Net_277 SETUP 3.510
Clock Skew 0.000
Net_255/q \NeoPixel:PrevSerClock\/main_0 122.085 MHz 8.191 12.642
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 Net_255 Net_255/clock_0 Net_255/q 1.250
Route 1 Net_255 Net_255/q \NeoPixel:PrevSerClock\/main_0 3.431
macrocell8 U(1,0) 1 \NeoPixel:PrevSerClock\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_275/q Net_279/main_4 40.746 MHz 24.542 17.125
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_275 Net_275/clock_0 Net_275/q 1.250
Route 1 Net_275 Net_275/q \NeoPixel:Datapath_1:u0\/cs_addr_1 3.151
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/cs_addr_1 \NeoPixel:Datapath_1:u0\/so_comb 13.180
Route 1 Net_310 \NeoPixel:Datapath_1:u0\/so_comb Net_279/main_4 3.451
macrocell2 U(1,1) 1 Net_279 SETUP 3.510
Clock Skew 0.000
Net_309/q Net_279/main_4 40.806 MHz 24.506 17.161
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,0) 1 Net_309 Net_309/clock_0 Net_309/q 1.250
Route 1 Net_309 Net_309/q \NeoPixel:Datapath_1:u0\/cs_addr_0 3.115
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/cs_addr_0 \NeoPixel:Datapath_1:u0\/so_comb 13.180
Route 1 Net_310 \NeoPixel:Datapath_1:u0\/so_comb Net_279/main_4 3.451
macrocell2 U(1,1) 1 Net_279 SETUP 3.510
Clock Skew 0.000
Net_276/q Net_279/main_4 41.004 MHz 24.388 17.279
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
Route 1 Net_276 Net_276/q \NeoPixel:Datapath_1:u0\/cs_addr_2 2.997
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/cs_addr_2 \NeoPixel:Datapath_1:u0\/so_comb 13.180
Route 1 Net_310 \NeoPixel:Datapath_1:u0\/so_comb Net_279/main_4 3.451
macrocell2 U(1,1) 1 Net_279 SETUP 3.510
Clock Skew 0.000
\NeoPixel:Datapath_1:u0\/so_comb Net_279/main_4 55.800 MHz 17.921 23.746
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/clock \NeoPixel:Datapath_1:u0\/so_comb 10.960
Route 1 Net_310 \NeoPixel:Datapath_1:u0\/so_comb Net_279/main_4 3.451
macrocell2 U(1,1) 1 Net_279 SETUP 3.510
Clock Skew 0.000
Net_275/q \NeoPixel:Datapath_1:u0\/cs_addr_1 62.771 MHz 15.931 25.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_275 Net_275/clock_0 Net_275/q 1.250
Route 1 Net_275 Net_275/q \NeoPixel:Datapath_1:u0\/cs_addr_1 3.151
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ SETUP 11.530
Clock Skew 0.000
Net_309/q \NeoPixel:Datapath_1:u0\/cs_addr_0 62.913 MHz 15.895 25.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,0) 1 Net_309 Net_309/clock_0 Net_309/q 1.250
Route 1 Net_309 Net_309/q \NeoPixel:Datapath_1:u0\/cs_addr_0 3.115
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ SETUP 11.530
Clock Skew 0.000
Net_276/q \NeoPixel:Datapath_1:u0\/cs_addr_2 63.383 MHz 15.777 25.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
Route 1 Net_276 Net_276/q \NeoPixel:Datapath_1:u0\/cs_addr_2 2.997
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ SETUP 11.530
Clock Skew 0.000
\NeoPixel:Datapath_1:u0\/f0_blk_stat_comb \NeoPixel:FIFO_Not_Empty\/main_3 77.688 MHz 12.872 28.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/clock \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb 5.280
Route 1 Net_287 \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb \NeoPixel:FIFO_Not_Empty\/main_3 4.082
macrocell9 U(0,1) 1 \NeoPixel:FIFO_Not_Empty\ SETUP 3.510
Clock Skew 0.000
\NeoPixel:Datapath_1:u0\/f0_blk_stat_comb Net_275/main_4 85.918 MHz 11.639 30.028
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/clock \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb 5.280
Route 1 Net_287 \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb Net_275/main_4 2.849
macrocell5 U(1,0) 1 Net_275 SETUP 3.510
Clock Skew 0.000
\NeoPixel:Datapath_1:u0\/f0_blk_stat_comb Net_276/main_4 85.918 MHz 11.639 30.028
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/clock \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb 5.280
Route 1 Net_287 \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb Net_276/main_4 2.849
macrocell6 U(1,0) 1 Net_276 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_255/q Net_277/main_0 25.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 Net_255 Net_255/clock_0 Net_255/q 1.250
Route 1 Net_255 Net_255/q Net_277/main_0 3.431
macrocell7 U(1,0) 1 Net_277 HOLD 0.000
Clock Skew 0.000
Net_255/q \NeoPixel:PrevSerClock\/main_0 25.514
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 Net_255 Net_255/clock_0 Net_255/q 1.250
Route 1 Net_255 Net_255/q \NeoPixel:PrevSerClock\/main_0 3.431
macrocell8 U(1,0) 1 \NeoPixel:PrevSerClock\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\NeoPixel:PrevSerClock\/q Net_277/main_1 3.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \NeoPixel:PrevSerClock\ \NeoPixel:PrevSerClock\/clock_0 \NeoPixel:PrevSerClock\/q 1.250
Route 1 \NeoPixel:PrevSerClock\ \NeoPixel:PrevSerClock\/q Net_277/main_1 2.227
macrocell7 U(1,0) 1 Net_277 HOLD 0.000
Clock Skew 0.000
\NeoPixel:SerEdge\/q \NeoPixel:SerEdge\/main_4 3.489
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \NeoPixel:SerEdge\ \NeoPixel:SerEdge\/clock_0 \NeoPixel:SerEdge\/q 1.250
macrocell10 U(1,0) 1 \NeoPixel:SerEdge\ \NeoPixel:SerEdge\/q \NeoPixel:SerEdge\/main_4 2.239
macrocell10 U(1,0) 1 \NeoPixel:SerEdge\ HOLD 0.000
Clock Skew 0.000
\NeoPixel:FIFO_Not_Empty\/q \NeoPixel:FIFO_Not_Empty\/main_4 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 \NeoPixel:FIFO_Not_Empty\ \NeoPixel:FIFO_Not_Empty\/clock_0 \NeoPixel:FIFO_Not_Empty\/q 1.250
macrocell9 U(0,1) 1 \NeoPixel:FIFO_Not_Empty\ \NeoPixel:FIFO_Not_Empty\/q \NeoPixel:FIFO_Not_Empty\/main_4 2.288
macrocell9 U(0,1) 1 \NeoPixel:FIFO_Not_Empty\ HOLD 0.000
Clock Skew 0.000
cy_tff_2/q \NeoPixel:FIFO_Not_Empty\/clk_en 3.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,1) 1 cy_tff_2 cy_tff_2/clock_0 cy_tff_2/q 1.250
Route 1 cy_tff_2 cy_tff_2/q \NeoPixel:FIFO_Not_Empty\/clk_en 2.317
macrocell9 U(0,1) 1 \NeoPixel:FIFO_Not_Empty\ HOLD 0.000
Clock Skew 0.000
Net_276/q Net_309/main_2 4.081
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
Route 1 Net_276 Net_276/q Net_309/main_2 2.831
macrocell4 U(1,0) 1 Net_309 HOLD 0.000
Clock Skew 0.000
Net_276/q Net_275/main_2 4.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
Route 1 Net_276 Net_276/q Net_275/main_2 2.985
macrocell5 U(1,0) 1 Net_275 HOLD 0.000
Clock Skew 0.000
Net_276/q Net_276/main_2 4.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
macrocell6 U(1,0) 1 Net_276 Net_276/q Net_276/main_2 2.985
macrocell6 U(1,0) 1 Net_276 HOLD 0.000
Clock Skew 0.000
Net_276/q \NeoPixel:SerEdge\/main_2 4.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
Route 1 Net_276 Net_276/q \NeoPixel:SerEdge\/main_2 2.985
macrocell10 U(1,0) 1 \NeoPixel:SerEdge\ HOLD 0.000
Clock Skew 0.000
Net_276/q \NeoPixel:Datapath_1:u0\/cs_addr_2 4.247
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
Route 1 Net_276 Net_276/q \NeoPixel:Datapath_1:u0\/cs_addr_2 2.997
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ HOLD 0.000
Clock Skew 0.000
Net_275/q Net_309/main_1 4.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_275 Net_275/clock_0 Net_275/q 1.250
Route 1 Net_275 Net_275/q Net_309/main_1 3.114
macrocell4 U(1,0) 1 Net_309 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ NeoClock
Source Destination Delay (ns)
Net_255/q Pin2_4MHz(0)_PAD 23.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 Net_255 Net_255/clock_0 Net_255/q 1.250
Route 1 Net_255 Net_255/q Pin2_4MHz(0)/pin_input 6.037
iocell2 P0[2] 1 Pin2_4MHz(0) Pin2_4MHz(0)/pin_input Pin2_4MHz(0)/pad_out 15.830
Route 1 Pin2_4MHz(0)_PAD Pin2_4MHz(0)/pad_out Pin2_4MHz(0)_PAD 0.000
Clock Clock path delay 0.000
+ UDBClock
Source Destination Delay (ns)
Net_275/q Shift_Value(0)_PAD 39.755
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_275 Net_275/clock_0 Net_275/q 1.250
Route 1 Net_275 Net_275/q \NeoPixel:Datapath_1:u0\/cs_addr_1 3.151
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/cs_addr_1 \NeoPixel:Datapath_1:u0\/so_comb 13.180
Route 1 Net_310 \NeoPixel:Datapath_1:u0\/so_comb Shift_Value(0)/pin_input 5.734
iocell10 P0[3] 1 Shift_Value(0) Shift_Value(0)/pin_input Shift_Value(0)/pad_out 16.440
Route 1 Shift_Value(0)_PAD Shift_Value(0)/pad_out Shift_Value(0)_PAD 0.000
Clock Clock path delay 0.000
\NeoPixel:Datapath_1:u0\/f0_blk_stat_comb FIFO_Empty(0)_PAD 30.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \NeoPixel:Datapath_1:u0\ \NeoPixel:Datapath_1:u0\/clock \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb 5.280
Route 1 Net_287 \NeoPixel:Datapath_1:u0\/f0_blk_stat_comb FIFO_Empty(0)/pin_input 6.434
iocell9 P2[3] 1 FIFO_Empty(0) FIFO_Empty(0)/pin_input FIFO_Empty(0)/pad_out 18.590
Route 1 FIFO_Empty(0)_PAD FIFO_Empty(0)/pad_out FIFO_Empty(0)_PAD 0.000
Clock Clock path delay 0.000
Net_309/q State0(0)_PAD 26.590
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,0) 1 Net_309 Net_309/clock_0 Net_309/q 1.250
Route 1 Net_309 Net_309/q State0(0)/pin_input 7.010
iocell1 P2[0] 1 State0(0) State0(0)/pin_input State0(0)/pad_out 18.330
Route 1 State0(0)_PAD State0(0)/pad_out State0(0)_PAD 0.000
Clock Clock path delay 0.000
Net_276/q State2(0)_PAD 25.145
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 Net_276 Net_276/clock_0 Net_276/q 1.250
Route 1 Net_276 Net_276/q State2(0)/pin_input 6.945
iocell7 P2[2] 1 State2(0) State2(0)/pin_input State2(0)/pad_out 16.950
Route 1 State2(0)_PAD State2(0)/pad_out State2(0)_PAD 0.000
Clock Clock path delay 0.000
Net_275/q State1(0)_PAD 25.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 Net_275 Net_275/clock_0 Net_275/q 1.250
Route 1 Net_275 Net_275/q State1(0)/pin_input 6.938
iocell6 P2[1] 1 State1(0) State1(0)/pin_input State1(0)/pad_out 16.910
Route 1 State1(0)_PAD State1(0)/pad_out State1(0)_PAD 0.000
Clock Clock path delay 0.000
cy_tff_2/q Pin12MHz(0)_PAD 23.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,1) 1 cy_tff_2 cy_tff_2/clock_0 cy_tff_2/q 1.250
Route 1 cy_tff_2 cy_tff_2/q Pin12MHz(0)/pin_input 6.209
iocell3 P1[5] 1 Pin12MHz(0) Pin12MHz(0)/pin_input Pin12MHz(0)/pad_out 16.480
Route 1 Pin12MHz(0)_PAD Pin12MHz(0)/pad_out Pin12MHz(0)_PAD 0.000
Clock Clock path delay 0.000
Net_277/q RiseEdge(0)_PAD 23.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,0) 1 Net_277 Net_277/clock_0 Net_277/q 1.250
Route 1 Net_277 Net_277/q RiseEdge(0)/pin_input 5.907
iocell8 P1[3] 1 RiseEdge(0) RiseEdge(0)/pin_input RiseEdge(0)/pad_out 16.590
Route 1 RiseEdge(0)_PAD RiseEdge(0)/pad_out RiseEdge(0)_PAD 0.000
Clock Clock path delay 0.000
Net_279/q SerOut(0)_PAD 23.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(1,1) 1 Net_279 Net_279/clock_0 Net_279/q 1.250
Route 1 Net_279 Net_279/q SerOut(0)/pin_input 6.226
iocell5 P0[1] 1 SerOut(0) SerOut(0)/pin_input SerOut(0)/pad_out 15.980
Route 1 SerOut(0)_PAD SerOut(0)/pad_out SerOut(0)_PAD 0.000
Clock Clock path delay 0.000
Net_245/q IdleOut(0)_PAD 22.531
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,1) 1 Net_245 Net_245/clock_0 Net_245/q 1.250
Route 1 Net_245 Net_245/q IdleOut(0)/pin_input 5.751
iocell4 P0[0] 1 IdleOut(0) IdleOut(0)/pin_input IdleOut(0)/pad_out 15.530
Route 1 IdleOut(0)_PAD IdleOut(0)/pad_out IdleOut(0)_PAD 0.000
Clock Clock path delay 0.000