# Static Timing Analysis

Project : | New_Garfield
Build Time : | 08/18/17 13:49:51
Device : | CYBLE-222014-01
Temperature : | -40C - 85C
VDDA : | 2.00
VDDA_CTB : | 2.00
VDDD_0 : | 2.00
VDDIO_0 : | 2.00
VDDIO_1 : | 2.00
VDDIO_2 : | 2.00
VDDR_BGLS : | 2.00
VDDR_HF : | 2.00
VDDR_HLS : | 2.00
VDDR_LF : | 2.00
VDDR_SYN : | 2.00
Voltage : | 2

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
ADC_intClock(FFB) | ADC_intClock(FFB) | 1.000 MHz | 1.000 MHz | N/A |
Clock_1(FFB) | Clock_1(FFB) | 32.000 kHz | 32.000 kHz | N/A |
CyECO | CyECO | 24.000 MHz | 24.000 MHz | N/A |
CyHFClk | CyHFClk | 48.000 MHz | 48.000 MHz | N/A |
SPI_SCBCLK | CyHFClk | 48.000 MHz | 48.000 MHz | N/A |
SCB_1_SCBCLK | CyHFClk | 1.371 MHz | 1.371 MHz | N/A |
ADC_intClock | CyHFClk | 1.000 MHz | 1.000 MHz | N/A |
Clock_1 | CyHFClk | 32.000 kHz | 32.000 kHz | N/A |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 48.000 MHz | 48.000 MHz | N/A |
CyLFClk | CyLFClk | 32.768 kHz | 32.768 kHz | N/A |
CyRouted1 | CyRouted1 | 48.000 MHz | 48.000 MHz | N/A |
CySysClk | CySysClk | 48.000 MHz | 48.000 MHz | N/A |
CyWCO | CyWCO | 32.768 kHz | 32.768 kHz | N/A |
SCB_1_SCBCLK(FFB) | SCB_1_SCBCLK(FFB) | 1.371 MHz | 1.371 MHz | N/A |
SPI_SCBCLK(FFB) | SPI_SCBCLK(FFB) | 48.000 MHz | 48.000 MHz | N/A |