Static Timing Analysis

Project : SimpleLCDFloat
Build Time : 08/26/16 12:19:52
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.50
VDDABUF : 5.50
VDDD : 5.50
VDDIO0 : 5.50
VDDIO1 : 5.50
VDDIO2 : 5.50
VDDIO3 : 5.50
VUSB : 5.50
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 6.000 MHz 6.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
CyXTAL_32kHz CyXTAL_32kHz 32.768 kHz 32.768 kHz N/A