Static Timing Analysis

Project : servo_c_code
Build Time : 09/23/13 10:44:49
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
UART_1_IntClock CyMASTER_CLK 461.538 kHz 461.538 kHz 41.769 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 44.133 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 44.133 MHz 22.659 19.008
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.038
macrocell10 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 64.098 MHz 15.601 26.066
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.931
macrocell8 U(3,3) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 64.098 MHz 15.601 26.066
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.931
macrocell11 U(3,3) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 64.608 MHz 15.478 26.189
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.808
macrocell12 U(3,3) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 64.641 MHz 15.470 26.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.800
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 67.990 MHz 14.708 26.959
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.038
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 67.990 MHz 14.708 26.959
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.038
macrocell15 U(3,4) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 2166.67ns(461.538 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 41.769 MHz 23.941 2142.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 4.914
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.907
datapathcell3 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.837 MHz 22.303 2144.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,5) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.276
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.907
datapathcell3 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.962 MHz 22.241 2144.426
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 3.214
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.907
datapathcell3 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.031 MHz 22.207 2144.460
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,5) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.180
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.907
datapathcell3 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 48.664 MHz 20.549 2146.118
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,4) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 2.302
macrocell19 U(2,4) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.927
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:rx_address_detected\/q \UART_1:BUART:sRX:RxBitCounter\/load 58.102 MHz 17.211 2149.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,5) 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/clock_0 \UART_1:BUART:rx_address_detected\/q 1.250
Route 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_counter_load\/main_0 6.082
macrocell7 U(3,3) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.309
count7cell U(3,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 60.768 MHz 16.456 2150.211
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 3.931
macrocell23 U(2,5) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.325
statusicell2 U(2,5) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 62.062 MHz 16.113 2150.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 3.402
macrocell10 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 64.779 MHz 15.437 2151.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.299
macrocell16 U(2,3) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 2.938
statusicell1 U(3,4) 1 \UART_1:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 64.906 MHz 15.407 2151.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,4) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 4.278
macrocell7 U(3,3) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.309
count7cell U(3,3) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 11.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.038
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 11.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.038
macrocell15 U(3,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 11.960
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.800
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 11.968
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.808
macrocell12 U(3,3) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 12.091
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.931
macrocell8 U(3,3) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 12.091
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.931
macrocell11 U(3,3) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 17.449
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell_ireg P0[0] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 6.160
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.038
macrocell10 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.313
statusicell1 U(3,4) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 3.535
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(3,3) 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/clock_0 \UART_1:BUART:rx_last\/q 1.250
Route 1 \UART_1:BUART:rx_last\ \UART_1:BUART:rx_last\/q \UART_1:BUART:rx_state_2\/main_9 2.285
macrocell12 U(3,3) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:pollcount_0\/main_3 2.287
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_status_3\/main_7 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,4) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_status_3\/main_7 2.287
macrocell15 U(3,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.849
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.599
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_state_stop1_reg\/main_0 3.888
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,5) 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/clock_0 \UART_1:BUART:rx_address_detected\/q 1.250
Route 1 \UART_1:BUART:rx_address_detected\ \UART_1:BUART:rx_address_detected\/q \UART_1:BUART:rx_state_stop1_reg\/main_0 2.638
macrocell14 U(3,5) 1 \UART_1:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 3.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:pollcount_1\/main_2 2.649
macrocell4 U(3,5) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_status_3\/main_2 4.023
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,4) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_status_3\/main_2 2.773
macrocell15 U(3,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 4.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,4) 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/clock_0 \UART_1:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART_1:BUART:rx_bitclk_enable\ \UART_1:BUART:rx_bitclk_enable\/q \UART_1:BUART:rx_state_3\/main_2 2.789
macrocell13 U(3,4) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:sRX:RxShifter:u0\/f0_load 4.055
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,3) 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/clock_0 \UART_1:BUART:rx_load_fifo\/q 1.250
Route 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:sRX:RxShifter:u0\/f0_load 2.805
datapathcell1 U(3,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 28.901
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 2.604
macrocell1 U(2,4) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx_1(0)/pin_input 5.497
iocell P0[1] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.200
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000