Static Timing Analysis

Project : LED_DRIVER
Build Time : 06/26/14 18:26:10
Device : CY8C5868LTI-LP039
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
mclk mclk -15.789
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_theACLK(fixed-function) ADC_SAR_theACLK(fixed-function) 1.818 MHz 1.818 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 60.000 MHz 60.000 MHz N/A
mclk CyMASTER_CLK 60.000 MHz 60.000 MHz 30.811 MHz Frequency
ADC_SAR_theACLK CyMASTER_CLK 1.818 MHz 1.818 MHz N/A
CyBUS_CLK CyMASTER_CLK 60.000 MHz 60.000 MHz 78.902 MHz
CyPLL_OUT CyPLL_OUT 60.000 MHz 60.000 MHz N/A
mclk(routed) mclk(routed) 60.000 MHz 60.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 16.6667ns(60 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_4\/ar_0 78.902 MHz 12.674 3.993
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_4\/ar_0 10.094
macrocell38 U(2,5) 1 \swGen:addr_4\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_10\/ar_0 85.121 MHz 11.748 4.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_10\/ar_0 9.168
macrocell26 U(3,4) 1 \swGen:addr_10\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_6\/ar_0 85.121 MHz 11.748 4.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_6\/ar_0 9.168
macrocell45 U(3,4) 1 \swGen:addr_6\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_9\/ar_0 92.430 MHz 10.819 5.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_9\/ar_0 8.239
macrocell62 U(2,3) 1 \swGen:addr_9\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_3\/ar_0 92.430 MHz 10.819 5.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_3\/ar_0 8.239
macrocell74 U(2,3) 1 \swGen:count_3\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_0\/ar_0 101.092 MHz 9.892 6.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_0\/ar_0 7.312
macrocell25 U(2,2) 1 \swGen:addr_0\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_2\/ar_0 101.092 MHz 9.892 6.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_2\/ar_0 7.312
macrocell36 U(2,2) 1 \swGen:addr_2\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_5\/ar_0 103.146 MHz 9.695 6.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_5\/ar_0 7.115
macrocell76 U(0,5) 1 \swGen:count_5\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_8\/ar_0 103.146 MHz 9.695 6.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_8\/ar_0 7.115
macrocell79 U(0,5) 1 \swGen:count_8\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:residue3_0\/ar_0 103.146 MHz 9.695 6.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:residue3_0\/ar_0 7.115
macrocell80 U(0,5) 1 \swGen:residue3_0\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 16.6667ns(60 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\swGen:addr_1\/q \swGen:addr_8\/main_0 30.811 MHz 32.456 -15.789 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,1) 1 \swGen:addr_1\ \swGen:addr_1\/clock_0 \swGen:addr_1\/q 1.250
Route 1 \swGen:addr_1\ \swGen:addr_1\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 9.826
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split\/main_11 4.390
macrocell56 U(2,2) 1 \swGen:addr_8_split\ \swGen:addr_8_split\/main_11 \swGen:addr_8_split\/q 3.350
Route 1 \swGen:addr_8_split\ \swGen:addr_8_split\/q \swGen:addr_8\/main_0 6.780
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_1\/q \swGen:addr_8\/main_1 31.633 MHz 31.613 -14.946 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,1) 1 \swGen:addr_1\ \swGen:addr_1\/clock_0 \swGen:addr_1\/q 1.250
Route 1 \swGen:addr_1\ \swGen:addr_1\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 9.826
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split_1\/main_11 7.435
macrocell57 U(0,2) 1 \swGen:addr_8_split_1\ \swGen:addr_8_split_1\/main_11 \swGen:addr_8_split_1\/q 3.350
Route 1 \swGen:addr_8_split_1\ \swGen:addr_8_split_1\/q \swGen:addr_8\/main_1 2.892
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_1\/q \swGen:addr_8\/main_3 31.703 MHz 31.543 -14.876 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,1) 1 \swGen:addr_1\ \swGen:addr_1\/clock_0 \swGen:addr_1\/q 1.250
Route 1 \swGen:addr_1\ \swGen:addr_1\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 9.826
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split_3\/main_11 7.320
macrocell59 U(1,4) 1 \swGen:addr_8_split_3\ \swGen:addr_8_split_3\/main_11 \swGen:addr_8_split_3\/q 3.350
Route 1 \swGen:addr_8_split_3\ \swGen:addr_8_split_3\/q \swGen:addr_8\/main_3 2.937
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_1\/q \swGen:addr_8\/main_2 31.993 MHz 31.257 -14.590 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,1) 1 \swGen:addr_1\ \swGen:addr_1\/clock_0 \swGen:addr_1\/q 1.250
Route 1 \swGen:addr_1\ \swGen:addr_1\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 9.826
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split_2\/main_11 3.180
macrocell58 U(2,4) 1 \swGen:addr_8_split_2\ \swGen:addr_8_split_2\/main_11 \swGen:addr_8_split_2\/q 3.350
Route 1 \swGen:addr_8_split_2\ \swGen:addr_8_split_2\/q \swGen:addr_8\/main_2 6.791
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_5\/q \swGen:addr_8\/main_0 32.211 MHz 31.045 -14.378 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,4) 1 \swGen:addr_5\ \swGen:addr_5\/clock_0 \swGen:addr_5\/q 1.250
Route 1 \swGen:addr_5\ \swGen:addr_5\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 8.415
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split\/main_11 4.390
macrocell56 U(2,2) 1 \swGen:addr_8_split\ \swGen:addr_8_split\/main_11 \swGen:addr_8_split\/q 3.350
Route 1 \swGen:addr_8_split\ \swGen:addr_8_split\/q \swGen:addr_8\/main_0 6.780
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_3\/q \swGen:addr_8\/main_0 32.603 MHz 30.672 -14.005 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(0,4) 1 \swGen:addr_3\ \swGen:addr_3\/clock_0 \swGen:addr_3\/q 1.250
Route 1 \swGen:addr_3\ \swGen:addr_3\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_4 8.042
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_4 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split\/main_11 4.390
macrocell56 U(2,2) 1 \swGen:addr_8_split\ \swGen:addr_8_split\/main_11 \swGen:addr_8_split\/q 3.350
Route 1 \swGen:addr_8_split\ \swGen:addr_8_split\/q \swGen:addr_8\/main_0 6.780
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_5\/q \swGen:addr_8\/main_1 33.110 MHz 30.202 -13.535 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,4) 1 \swGen:addr_5\ \swGen:addr_5\/clock_0 \swGen:addr_5\/q 1.250
Route 1 \swGen:addr_5\ \swGen:addr_5\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 8.415
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split_1\/main_11 7.435
macrocell57 U(0,2) 1 \swGen:addr_8_split_1\ \swGen:addr_8_split_1\/main_11 \swGen:addr_8_split_1\/q 3.350
Route 1 \swGen:addr_8_split_1\ \swGen:addr_8_split_1\/q \swGen:addr_8\/main_1 2.892
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_5\/q \swGen:addr_8\/main_3 33.187 MHz 30.132 -13.465 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,4) 1 \swGen:addr_5\ \swGen:addr_5\/clock_0 \swGen:addr_5\/q 1.250
Route 1 \swGen:addr_5\ \swGen:addr_5\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 8.415
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split_3\/main_11 7.320
macrocell59 U(1,4) 1 \swGen:addr_8_split_3\ \swGen:addr_8_split_3\/main_11 \swGen:addr_8_split_3\/q 3.350
Route 1 \swGen:addr_8_split_3\ \swGen:addr_8_split_3\/q \swGen:addr_8\/main_3 2.937
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_1\/q \swGen:addr_8\/main_5 33.193 MHz 30.127 -13.460 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,1) 1 \swGen:addr_1\ \swGen:addr_1\/clock_0 \swGen:addr_1\/q 1.250
Route 1 \swGen:addr_1\ \swGen:addr_1\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 9.826
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_6 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split_5\/main_10 6.545
macrocell61 U(0,3) 1 \swGen:addr_8_split_5\ \swGen:addr_8_split_5\/main_10 \swGen:addr_8_split_5\/q 3.350
Route 1 \swGen:addr_8_split_5\ \swGen:addr_8_split_5\/q \swGen:addr_8\/main_5 2.296
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
\swGen:addr_5\/q \swGen:addr_8\/main_2 33.505 MHz 29.846 -13.179 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,4) 1 \swGen:addr_5\ \swGen:addr_5\/clock_0 \swGen:addr_5\/q 1.250
Route 1 \swGen:addr_5\ \swGen:addr_5\/q \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 8.415
macrocell22 U(2,3) 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/main_2 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q 3.350
Route 1 \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\ \swGen:MODULE_1:g2:a0:g1:z1:s0:g1:u0:b_8\/q \swGen:addr_8_split_2\/main_11 3.180
macrocell58 U(2,4) 1 \swGen:addr_8_split_2\ \swGen:addr_8_split_2\/main_11 \swGen:addr_8_split_2\/q 3.350
Route 1 \swGen:addr_8_split_2\ \swGen:addr_8_split_2\/q \swGen:addr_8\/main_2 6.791
macrocell55 U(1,3) 1 \swGen:addr_8\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_1\/ar_0 5.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_1\/ar_0 3.406
macrocell30 U(0,1) 1 \swGen:addr_1\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_4\/ar_0 7.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_4\/ar_0 5.260
macrocell75 U(0,3) 1 \swGen:count_4\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_7\/ar_0 7.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_7\/ar_0 5.260
macrocell78 U(0,3) 1 \swGen:count_7\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_7\/ar_0 7.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_7\/ar_0 5.261
macrocell50 U(1,3) 1 \swGen:addr_7\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_8\/ar_0 7.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_8\/ar_0 5.261
macrocell55 U(1,3) 1 \swGen:addr_8\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_1\/ar_0 7.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_1\/ar_0 5.261
macrocell72 U(1,3) 1 \swGen:count_1\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_3\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_3\/ar_0 6.188
macrocell37 U(0,4) 1 \swGen:addr_3\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_5\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_5\/ar_0 6.188
macrocell40 U(0,4) 1 \swGen:addr_5\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_0\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_0\/ar_0 6.188
macrocell71 U(0,4) 1 \swGen:count_0\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_2\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_2\/ar_0 6.188
macrocell73 U(0,4) 1 \swGen:count_2\ REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\DPWM:PWMUDB:status_0\/q \DPWM:PWMUDB:genblk8:stsreg\/status_0 1.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,1) 1 \DPWM:PWMUDB:status_0\ \DPWM:PWMUDB:status_0\/clock_0 \DPWM:PWMUDB:status_0\/q 1.250
Route 1 \DPWM:PWMUDB:status_0\ \DPWM:PWMUDB:status_0\/q \DPWM:PWMUDB:genblk8:stsreg\/status_0 2.316
statusicell1 U(1,1) 1 \DPWM:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\DPWM:PWMUDB:sP16:pwmdp:u0\/co_msb \DPWM:PWMUDB:sP16:pwmdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \DPWM:PWMUDB:sP16:pwmdp:u0\ \DPWM:PWMUDB:sP16:pwmdp:u0\/clock \DPWM:PWMUDB:sP16:pwmdp:u0\/co_msb 3.210
Route 1 \DPWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \DPWM:PWMUDB:sP16:pwmdp:u0\/co_msb \DPWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \DPWM:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\DPWM:PWMUDB:prevCompare1\/q \DPWM:PWMUDB:status_0\/main_0 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \DPWM:PWMUDB:prevCompare1\ \DPWM:PWMUDB:prevCompare1\/clock_0 \DPWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \DPWM:PWMUDB:prevCompare1\ \DPWM:PWMUDB:prevCompare1\/q \DPWM:PWMUDB:status_0\/main_0 2.308
macrocell20 U(0,1) 1 \DPWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\swGen:residue3_1\/q \swGen:residue3_0\/main_9 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell81 U(0,5) 1 \swGen:residue3_1\ \swGen:residue3_1\/clock_0 \swGen:residue3_1\/q 1.250
Route 1 \swGen:residue3_1\ \swGen:residue3_1\/q \swGen:residue3_0\/main_9 2.782
macrocell80 U(0,5) 1 \swGen:residue3_0\ HOLD 0.000
Clock Skew 0.000
\swGen:residue3_1\/q \swGen:residue3_1\/main_9 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell81 U(0,5) 1 \swGen:residue3_1\ \swGen:residue3_1\/clock_0 \swGen:residue3_1\/q 1.250
macrocell81 U(0,5) 1 \swGen:residue3_1\ \swGen:residue3_1\/q \swGen:residue3_1\/main_9 2.782
macrocell81 U(0,5) 1 \swGen:residue3_1\ HOLD 0.000
Clock Skew 0.000
\DPWM:PWMUDB:genblk1:ctrlreg\/control_7 Net_342/main_0 4.288
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,0) 1 \DPWM:PWMUDB:genblk1:ctrlreg\ \DPWM:PWMUDB:genblk1:ctrlreg\/clock \DPWM:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \DPWM:PWMUDB:control_7\ \DPWM:PWMUDB:genblk1:ctrlreg\/control_7 Net_342/main_0 2.248
macrocell15 U(2,0) 1 Net_342 HOLD 0.000
Clock Skew 0.000
\DPWM:PWMUDB:genblk1:ctrlreg\/control_7 \DPWM:PWMUDB:runmode_enable\/main_0 4.288
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,0) 1 \DPWM:PWMUDB:genblk1:ctrlreg\ \DPWM:PWMUDB:genblk1:ctrlreg\/clock \DPWM:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \DPWM:PWMUDB:control_7\ \DPWM:PWMUDB:genblk1:ctrlreg\/control_7 \DPWM:PWMUDB:runmode_enable\/main_0 2.248
macrocell19 U(2,0) 1 \DPWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\swGen:count_7\/q \swGen:count_4\/main_1 4.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell78 U(0,3) 1 \swGen:count_7\ \swGen:count_7\/clock_0 \swGen:count_7\/q 1.250
Route 1 \swGen:count_7\ \swGen:count_7\/q \swGen:count_4\/main_1 3.416
macrocell75 U(0,3) 1 \swGen:count_4\ HOLD 0.000
Clock Skew 0.000
\swGen:count_7\/q \swGen:count_7\/main_1 4.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell78 U(0,3) 1 \swGen:count_7\ \swGen:count_7\/clock_0 \swGen:count_7\/q 1.250
macrocell78 U(0,3) 1 \swGen:count_7\ \swGen:count_7\/q \swGen:count_7\/main_1 3.416
macrocell78 U(0,3) 1 \swGen:count_7\ HOLD 0.000
Clock Skew 0.000
\swGen:addr_0\/q \swGen:addr_2\/main_10 4.676
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,2) 1 \swGen:addr_0\ \swGen:addr_0\/clock_0 \swGen:addr_0\/q 1.250
Route 1 \swGen:addr_0\ \swGen:addr_0\/q \swGen:addr_2\/main_10 3.426
macrocell36 U(2,2) 1 \swGen:addr_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_0 reserve(0)_PAD 25.762
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 reserve(0)/pin_input 6.962
iocell5 P12[6] 1 reserve(0) reserve(0)/pin_input reserve(0)/pad_out 16.220
Route 1 reserve(0)_PAD reserve(0)/pad_out reserve(0)_PAD 0.000
Clock Clock path delay 0.000
+ mclk
Source Destination Delay (ns)
\swGen:addr_4\/q gate3(0)_PAD 78.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,5) 1 \swGen:addr_4\ \swGen:addr_4\/clock_0 \swGen:addr_4\/q 1.250
Route 1 \swGen:addr_4\ \swGen:addr_4\/q \swGen:cmp_vv_vv_MODGEN_8\/main_6 21.926
macrocell69 U(3,0) 1 \swGen:cmp_vv_vv_MODGEN_8\ \swGen:cmp_vv_vv_MODGEN_8\/main_6 \swGen:cmp_vv_vv_MODGEN_8\/q 3.350
Route 1 \swGen:cmp_vv_vv_MODGEN_8\ \swGen:cmp_vv_vv_MODGEN_8\/q Net_293_split_3/main_5 15.112
macrocell13 U(3,2) 1 Net_293_split_3 Net_293_split_3/main_5 Net_293_split_3/q 3.350
Route 1 Net_293_split_3 Net_293_split_3/q Net_293/main_3 6.382
macrocell9 U(1,1) 1 Net_293 Net_293/main_3 Net_293/q 3.350
Route 1 Net_293 Net_293/q gate3(0)/pin_input 8.128
iocell4 P2[2] 1 gate3(0) gate3(0)/pin_input gate3(0)/pad_out 15.787
Route 1 gate3(0)_PAD gate3(0)/pad_out gate3(0)_PAD 0.000
Clock Clock path delay 0.000
\swGen:addr_4\/q gate2(0)_PAD 76.771
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,5) 1 \swGen:addr_4\ \swGen:addr_4\/clock_0 \swGen:addr_4\/q 1.250
Route 1 \swGen:addr_4\ \swGen:addr_4\/q \swGen:cmp_vv_vv_MODGEN_10\/main_6 21.381
macrocell63 U(3,0) 1 \swGen:cmp_vv_vv_MODGEN_10\ \swGen:cmp_vv_vv_MODGEN_10\/main_6 \swGen:cmp_vv_vv_MODGEN_10\/q 3.350
Route 1 \swGen:cmp_vv_vv_MODGEN_10\ \swGen:cmp_vv_vv_MODGEN_10\/q Net_292_split_1/main_7 18.186
macrocell7 U(3,5) 1 Net_292_split_1 Net_292_split_1/main_7 Net_292_split_1/q 3.350
Route 1 Net_292_split_1 Net_292_split_1/q Net_292/main_5 2.915
macrocell5 U(3,4) 1 Net_292 Net_292/main_5 Net_292/q 3.350
Route 1 Net_292 Net_292/q gate2(0)/pin_input 7.098
iocell3 P2[1] 1 gate2(0) gate2(0)/pin_input gate2(0)/pad_out 15.891
Route 1 gate2(0)_PAD gate2(0)/pad_out gate2(0)_PAD 0.000
Clock Clock path delay 0.000
\swGen:addr_4\/q gate1(0)_PAD 73.134
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,5) 1 \swGen:addr_4\ \swGen:addr_4\/clock_0 \swGen:addr_4\/q 1.250
Route 1 \swGen:addr_4\ \swGen:addr_4\/q \swGen:cmp_vv_vv_MODGEN_10\/main_6 21.381
macrocell63 U(3,0) 1 \swGen:cmp_vv_vv_MODGEN_10\ \swGen:cmp_vv_vv_MODGEN_10\/main_6 \swGen:cmp_vv_vv_MODGEN_10\/q 3.350
Route 1 \swGen:cmp_vv_vv_MODGEN_10\ \swGen:cmp_vv_vv_MODGEN_10\/q Net_291_split_2/main_7 14.366
macrocell4 U(1,4) 1 Net_291_split_2 Net_291_split_2/main_7 Net_291_split_2/q 3.350
Route 1 Net_291_split_2 Net_291_split_2/q Net_291/main_2 3.681
macrocell1 U(1,2) 1 Net_291 Net_291/main_2 Net_291/q 3.350
Route 1 Net_291 Net_291/q gate1(0)/pin_input 6.739
iocell2 P2[0] 1 gate1(0) gate1(0)/pin_input gate1(0)/pad_out 15.667
Route 1 gate1(0)_PAD gate1(0)/pad_out gate1(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 16.6667ns(60 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_4\/ar_0 78.902 MHz 12.674 3.993
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_4\/ar_0 10.094
macrocell38 U(2,5) 1 \swGen:addr_4\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_10\/ar_0 85.121 MHz 11.748 4.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_10\/ar_0 9.168
macrocell26 U(3,4) 1 \swGen:addr_10\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_6\/ar_0 85.121 MHz 11.748 4.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_6\/ar_0 9.168
macrocell45 U(3,4) 1 \swGen:addr_6\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_9\/ar_0 92.430 MHz 10.819 5.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_9\/ar_0 8.239
macrocell62 U(2,3) 1 \swGen:addr_9\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_3\/ar_0 92.430 MHz 10.819 5.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_3\/ar_0 8.239
macrocell74 U(2,3) 1 \swGen:count_3\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_0\/ar_0 101.092 MHz 9.892 6.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_0\/ar_0 7.312
macrocell25 U(2,2) 1 \swGen:addr_0\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_2\/ar_0 101.092 MHz 9.892 6.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_2\/ar_0 7.312
macrocell36 U(2,2) 1 \swGen:addr_2\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_5\/ar_0 103.146 MHz 9.695 6.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_5\/ar_0 7.115
macrocell76 U(0,5) 1 \swGen:count_5\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_8\/ar_0 103.146 MHz 9.695 6.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_8\/ar_0 7.115
macrocell79 U(0,5) 1 \swGen:count_8\ RECOVERY -0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:residue3_0\/ar_0 103.146 MHz 9.695 6.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:residue3_0\/ar_0 7.115
macrocell80 U(0,5) 1 \swGen:residue3_0\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_1\/ar_0 5.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_1\/ar_0 3.406
macrocell30 U(0,1) 1 \swGen:addr_1\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_4\/ar_0 7.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_4\/ar_0 5.260
macrocell75 U(0,3) 1 \swGen:count_4\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_7\/ar_0 7.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_7\/ar_0 5.260
macrocell78 U(0,3) 1 \swGen:count_7\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_7\/ar_0 7.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_7\/ar_0 5.261
macrocell50 U(1,3) 1 \swGen:addr_7\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_8\/ar_0 7.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_8\/ar_0 5.261
macrocell55 U(1,3) 1 \swGen:addr_8\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_1\/ar_0 7.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_1\/ar_0 5.261
macrocell72 U(1,3) 1 \swGen:count_1\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_3\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_3\/ar_0 6.188
macrocell37 U(0,4) 1 \swGen:addr_3\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_5\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:addr_5\/ar_0 6.188
macrocell40 U(0,4) 1 \swGen:addr_5\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_0\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_0\/ar_0 6.188
macrocell71 U(0,4) 1 \swGen:count_0\ REMOVAL 0.000
Clock Skew 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_2\/ar_0 8.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_488 \Control_Reg_1:Sync:ctrl_reg\/control_0 \swGen:count_2\/ar_0 6.188
macrocell73 U(0,4) 1 \swGen:count_2\ REMOVAL 0.000
Clock Skew 0.000