/*******************************************************************************
* File Name: cyfitter.h
* 
* PSoC Creator  4.1 Update 1
*
* Description:
* 
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice_trm.h"

/* ADC */
#define ADC_cy_psoc4_sar__CLOCK_DIV_ID 0x00000041u
#define ADC_cy_psoc4_sar__SAR_ANA_TRIM CYREG_SAR_ANA_TRIM
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG00 CYREG_SAR_CHAN_CONFIG0
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG01 CYREG_SAR_CHAN_CONFIG1
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG02 CYREG_SAR_CHAN_CONFIG2
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG03 CYREG_SAR_CHAN_CONFIG3
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG04 CYREG_SAR_CHAN_CONFIG4
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG05 CYREG_SAR_CHAN_CONFIG5
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG06 CYREG_SAR_CHAN_CONFIG6
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG07 CYREG_SAR_CHAN_CONFIG7
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG08 CYREG_SAR_CHAN_CONFIG8
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG09 CYREG_SAR_CHAN_CONFIG9
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG10 CYREG_SAR_CHAN_CONFIG10
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG11 CYREG_SAR_CHAN_CONFIG11
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG12 CYREG_SAR_CHAN_CONFIG12
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG13 CYREG_SAR_CHAN_CONFIG13
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG14 CYREG_SAR_CHAN_CONFIG14
#define ADC_cy_psoc4_sar__SAR_CHAN_CONFIG15 CYREG_SAR_CHAN_CONFIG15
#define ADC_cy_psoc4_sar__SAR_CHAN_EN CYREG_SAR_CHAN_EN
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT_VALID CYREG_SAR_CHAN_RESULT_VALID
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT00 CYREG_SAR_CHAN_RESULT0
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT01 CYREG_SAR_CHAN_RESULT1
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT02 CYREG_SAR_CHAN_RESULT2
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT03 CYREG_SAR_CHAN_RESULT3
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT04 CYREG_SAR_CHAN_RESULT4
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT05 CYREG_SAR_CHAN_RESULT5
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT06 CYREG_SAR_CHAN_RESULT6
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT07 CYREG_SAR_CHAN_RESULT7
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT08 CYREG_SAR_CHAN_RESULT8
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT09 CYREG_SAR_CHAN_RESULT9
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT10 CYREG_SAR_CHAN_RESULT10
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT11 CYREG_SAR_CHAN_RESULT11
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT12 CYREG_SAR_CHAN_RESULT12
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT13 CYREG_SAR_CHAN_RESULT13
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT14 CYREG_SAR_CHAN_RESULT14
#define ADC_cy_psoc4_sar__SAR_CHAN_RESULT15 CYREG_SAR_CHAN_RESULT15
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK_VALID CYREG_SAR_CHAN_WORK_VALID
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK00 CYREG_SAR_CHAN_WORK0
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK01 CYREG_SAR_CHAN_WORK1
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK02 CYREG_SAR_CHAN_WORK2
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK03 CYREG_SAR_CHAN_WORK3
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK04 CYREG_SAR_CHAN_WORK4
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK05 CYREG_SAR_CHAN_WORK5
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK06 CYREG_SAR_CHAN_WORK6
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK07 CYREG_SAR_CHAN_WORK7
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK08 CYREG_SAR_CHAN_WORK8
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK09 CYREG_SAR_CHAN_WORK9
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK10 CYREG_SAR_CHAN_WORK10
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK11 CYREG_SAR_CHAN_WORK11
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK12 CYREG_SAR_CHAN_WORK12
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK13 CYREG_SAR_CHAN_WORK13
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK14 CYREG_SAR_CHAN_WORK14
#define ADC_cy_psoc4_sar__SAR_CHAN_WORK15 CYREG_SAR_CHAN_WORK15
#define ADC_cy_psoc4_sar__SAR_CTRL CYREG_SAR_CTRL
#define ADC_cy_psoc4_sar__SAR_DFT_CTRL CYREG_SAR_DFT_CTRL
#define ADC_cy_psoc4_sar__SAR_INTR CYREG_SAR_INTR
#define ADC_cy_psoc4_sar__SAR_INTR_CAUSE CYREG_SAR_INTR_CAUSE
#define ADC_cy_psoc4_sar__SAR_INTR_MASK CYREG_SAR_INTR_MASK
#define ADC_cy_psoc4_sar__SAR_INTR_MASKED CYREG_SAR_INTR_MASKED
#define ADC_cy_psoc4_sar__SAR_INTR_SET CYREG_SAR_INTR_SET
#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH_HW_CTRL CYREG_SAR_MUX_SWITCH_HW_CTRL
#define ADC_cy_psoc4_sar__SAR_MUX_SWITCH0 CYREG_SAR_MUX_SWITCH0
#define ADC_cy_psoc4_sar__SAR_NUMBER 0u
#define ADC_cy_psoc4_sar__SAR_PUMP_CTRL CYREG_SAR_PUMP_CTRL
#define ADC_cy_psoc4_sar__SAR_RANGE_COND CYREG_SAR_RANGE_COND
#define ADC_cy_psoc4_sar__SAR_RANGE_INTR CYREG_SAR_RANGE_INTR
#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASK CYREG_SAR_RANGE_INTR_MASK
#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_MASKED CYREG_SAR_RANGE_INTR_MASKED
#define ADC_cy_psoc4_sar__SAR_RANGE_INTR_SET CYREG_SAR_RANGE_INTR_SET
#define ADC_cy_psoc4_sar__SAR_RANGE_THRES CYREG_SAR_RANGE_THRES
#define ADC_cy_psoc4_sar__SAR_SAMPLE_CTRL CYREG_SAR_SAMPLE_CTRL
#define ADC_cy_psoc4_sar__SAR_SAMPLE_TIME01 CYREG_SAR_SAMPLE_TIME01
#define ADC_cy_psoc4_sar__SAR_SAMPLE_TIME23 CYREG_SAR_SAMPLE_TIME23
#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR CYREG_SAR_SATURATE_INTR
#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASK CYREG_SAR_SATURATE_INTR_MASK
#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED CYREG_SAR_SATURATE_INTR_MASKED
#define ADC_cy_psoc4_sar__SAR_SATURATE_INTR_SET CYREG_SAR_SATURATE_INTR_SET
#define ADC_cy_psoc4_sar__SAR_START_CTRL CYREG_SAR_START_CTRL
#define ADC_cy_psoc4_sar__SAR_STATUS CYREG_SAR_STATUS
#define ADC_cy_psoc4_sar__SAR_WOUNDING CYREG_SAR_WOUNDING
#define ADC_intClock__CTRL_REGISTER CYREG_PERI_PCLK_CTL6
#define ADC_intClock__DIV_ID 0x00000041u
#define ADC_intClock__DIV_REGISTER CYREG_PERI_DIV_16_CTL1
#define ADC_intClock__PA_DIV_ID 0x000000FFu
#define ADC_IRQ__INTC_CLR_EN_REG CYREG_CM0_ICER
#define ADC_IRQ__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define ADC_IRQ__INTC_MASK 0x8000u
#define ADC_IRQ__INTC_NUMBER 15u
#define ADC_IRQ__INTC_PRIOR_MASK 0xC0000000u
#define ADC_IRQ__INTC_PRIOR_NUM 3u
#define ADC_IRQ__INTC_PRIOR_REG CYREG_CM0_IPR3
#define ADC_IRQ__INTC_SET_EN_REG CYREG_CM0_ISER
#define ADC_IRQ__INTC_SET_PD_REG CYREG_CM0_ISPR

/* FiltInt */
#define FiltInt__INTC_CLR_EN_REG CYREG_CM0_ICER
#define FiltInt__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define FiltInt__INTC_MASK 0x02u
#define FiltInt__INTC_NUMBER 1u
#define FiltInt__INTC_PRIOR_MASK 0xC000u
#define FiltInt__INTC_PRIOR_NUM 3u
#define FiltInt__INTC_PRIOR_REG CYREG_CM0_IPR0
#define FiltInt__INTC_SET_EN_REG CYREG_CM0_ISER
#define FiltInt__INTC_SET_PD_REG CYREG_CM0_ISPR

/* FiltReset */
#define FiltReset_Sync_ctrl_reg__0__MASK 0x01u
#define FiltReset_Sync_ctrl_reg__0__POS 0
#define FiltReset_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_UDB_W16_ACTL1
#define FiltReset_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_UDB_W16_CTL1
#define FiltReset_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_UDB_W16_CTL1
#define FiltReset_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_UDB_W16_CTL1
#define FiltReset_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_UDB_W16_CTL1
#define FiltReset_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_UDB_W16_MSK1
#define FiltReset_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_UDB_W16_MSK1
#define FiltReset_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_UDB_W16_MSK1
#define FiltReset_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_UDB_W16_MSK1
#define FiltReset_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_UDB_W8_ACTL1
#define FiltReset_Sync_ctrl_reg__CONTROL_REG CYREG_UDB_W8_CTL1
#define FiltReset_Sync_ctrl_reg__CONTROL_ST_REG CYREG_UDB_CAT16_CTL_ST1
#define FiltReset_Sync_ctrl_reg__COUNT_REG CYREG_UDB_W8_CTL1
#define FiltReset_Sync_ctrl_reg__COUNT_ST_REG CYREG_UDB_CAT16_CTL_ST1
#define FiltReset_Sync_ctrl_reg__MASK 0x01u
#define FiltReset_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK1
#define FiltReset_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK1
#define FiltReset_Sync_ctrl_reg__PERIOD_REG CYREG_UDB_W8_MSK1

/* IDAC */
#define IDAC_cy_psoc4_idac__CONTROL CYREG_CSD_CONFIG
#define IDAC_cy_psoc4_idac__CSD_IDAC CYREG_CSD_IDAC
#define IDAC_cy_psoc4_idac__CSD_IDAC_SHIFT 0u
#define IDAC_cy_psoc4_idac__CSD_TRIM1 CYREG_CSD_TRIM1
#define IDAC_cy_psoc4_idac__CSD_TRIM1_SHIFT 0u
#define IDAC_cy_psoc4_idac__CSD_TRIM2 CYREG_CSD_TRIM2
#define IDAC_cy_psoc4_idac__CSD_TRIM2_SHIFT 0u
#define IDAC_cy_psoc4_idac__IDAC_NUMBER 1u
#define IDAC_cy_psoc4_idac__POLARITY CYREG_CSD_CONFIG
#define IDAC_cy_psoc4_idac__POLARITY_SHIFT 16u

/* PIN_BLUE */
#define PIN_BLUE__0__DR CYREG_GPIO_PRT3_DR
#define PIN_BLUE__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define PIN_BLUE__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define PIN_BLUE__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define PIN_BLUE__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define PIN_BLUE__0__HSIOM_MASK 0xF0000000u
#define PIN_BLUE__0__HSIOM_SHIFT 28u
#define PIN_BLUE__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define PIN_BLUE__0__INTR CYREG_GPIO_PRT3_INTR
#define PIN_BLUE__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define PIN_BLUE__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define PIN_BLUE__0__MASK 0x80u
#define PIN_BLUE__0__OUT_SEL CYREG_UDB_PA3_CFG10
#define PIN_BLUE__0__OUT_SEL_SHIFT 14u
#define PIN_BLUE__0__OUT_SEL_VAL -1u
#define PIN_BLUE__0__PA__CFG0 CYREG_UDB_PA3_CFG0
#define PIN_BLUE__0__PA__CFG1 CYREG_UDB_PA3_CFG1
#define PIN_BLUE__0__PA__CFG10 CYREG_UDB_PA3_CFG10
#define PIN_BLUE__0__PA__CFG11 CYREG_UDB_PA3_CFG11
#define PIN_BLUE__0__PA__CFG12 CYREG_UDB_PA3_CFG12
#define PIN_BLUE__0__PA__CFG13 CYREG_UDB_PA3_CFG13
#define PIN_BLUE__0__PA__CFG14 CYREG_UDB_PA3_CFG14
#define PIN_BLUE__0__PA__CFG2 CYREG_UDB_PA3_CFG2
#define PIN_BLUE__0__PA__CFG3 CYREG_UDB_PA3_CFG3
#define PIN_BLUE__0__PA__CFG4 CYREG_UDB_PA3_CFG4
#define PIN_BLUE__0__PA__CFG5 CYREG_UDB_PA3_CFG5
#define PIN_BLUE__0__PA__CFG6 CYREG_UDB_PA3_CFG6
#define PIN_BLUE__0__PA__CFG7 CYREG_UDB_PA3_CFG7
#define PIN_BLUE__0__PA__CFG8 CYREG_UDB_PA3_CFG8
#define PIN_BLUE__0__PA__CFG9 CYREG_UDB_PA3_CFG9
#define PIN_BLUE__0__PC CYREG_GPIO_PRT3_PC
#define PIN_BLUE__0__PC2 CYREG_GPIO_PRT3_PC2
#define PIN_BLUE__0__PORT 3u
#define PIN_BLUE__0__PS CYREG_GPIO_PRT3_PS
#define PIN_BLUE__0__SHIFT 7u
#define PIN_BLUE__DR CYREG_GPIO_PRT3_DR
#define PIN_BLUE__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define PIN_BLUE__DR_INV CYREG_GPIO_PRT3_DR_INV
#define PIN_BLUE__DR_SET CYREG_GPIO_PRT3_DR_SET
#define PIN_BLUE__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define PIN_BLUE__INTR CYREG_GPIO_PRT3_INTR
#define PIN_BLUE__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define PIN_BLUE__INTSTAT CYREG_GPIO_PRT3_INTR
#define PIN_BLUE__MASK 0x80u
#define PIN_BLUE__PA__CFG0 CYREG_UDB_PA3_CFG0
#define PIN_BLUE__PA__CFG1 CYREG_UDB_PA3_CFG1
#define PIN_BLUE__PA__CFG10 CYREG_UDB_PA3_CFG10
#define PIN_BLUE__PA__CFG11 CYREG_UDB_PA3_CFG11
#define PIN_BLUE__PA__CFG12 CYREG_UDB_PA3_CFG12
#define PIN_BLUE__PA__CFG13 CYREG_UDB_PA3_CFG13
#define PIN_BLUE__PA__CFG14 CYREG_UDB_PA3_CFG14
#define PIN_BLUE__PA__CFG2 CYREG_UDB_PA3_CFG2
#define PIN_BLUE__PA__CFG3 CYREG_UDB_PA3_CFG3
#define PIN_BLUE__PA__CFG4 CYREG_UDB_PA3_CFG4
#define PIN_BLUE__PA__CFG5 CYREG_UDB_PA3_CFG5
#define PIN_BLUE__PA__CFG6 CYREG_UDB_PA3_CFG6
#define PIN_BLUE__PA__CFG7 CYREG_UDB_PA3_CFG7
#define PIN_BLUE__PA__CFG8 CYREG_UDB_PA3_CFG8
#define PIN_BLUE__PA__CFG9 CYREG_UDB_PA3_CFG9
#define PIN_BLUE__PC CYREG_GPIO_PRT3_PC
#define PIN_BLUE__PC2 CYREG_GPIO_PRT3_PC2
#define PIN_BLUE__PORT 3u
#define PIN_BLUE__PS CYREG_GPIO_PRT3_PS
#define PIN_BLUE__SHIFT 7u

/* PIN_RED */
#define PIN_RED__0__DR CYREG_GPIO_PRT2_DR
#define PIN_RED__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define PIN_RED__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define PIN_RED__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define PIN_RED__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define PIN_RED__0__HSIOM_MASK 0x0F000000u
#define PIN_RED__0__HSIOM_SHIFT 24u
#define PIN_RED__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define PIN_RED__0__INTR CYREG_GPIO_PRT2_INTR
#define PIN_RED__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define PIN_RED__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define PIN_RED__0__MASK 0x40u
#define PIN_RED__0__OUT_SEL CYREG_UDB_PA2_CFG10
#define PIN_RED__0__OUT_SEL_SHIFT 12u
#define PIN_RED__0__OUT_SEL_VAL 1u
#define PIN_RED__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define PIN_RED__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define PIN_RED__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define PIN_RED__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define PIN_RED__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define PIN_RED__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define PIN_RED__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define PIN_RED__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define PIN_RED__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define PIN_RED__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define PIN_RED__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define PIN_RED__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define PIN_RED__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define PIN_RED__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define PIN_RED__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define PIN_RED__0__PC CYREG_GPIO_PRT2_PC
#define PIN_RED__0__PC2 CYREG_GPIO_PRT2_PC2
#define PIN_RED__0__PORT 2u
#define PIN_RED__0__PS CYREG_GPIO_PRT2_PS
#define PIN_RED__0__SHIFT 6u
#define PIN_RED__DR CYREG_GPIO_PRT2_DR
#define PIN_RED__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define PIN_RED__DR_INV CYREG_GPIO_PRT2_DR_INV
#define PIN_RED__DR_SET CYREG_GPIO_PRT2_DR_SET
#define PIN_RED__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define PIN_RED__INTR CYREG_GPIO_PRT2_INTR
#define PIN_RED__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define PIN_RED__INTSTAT CYREG_GPIO_PRT2_INTR
#define PIN_RED__MASK 0x40u
#define PIN_RED__PA__CFG0 CYREG_UDB_PA2_CFG0
#define PIN_RED__PA__CFG1 CYREG_UDB_PA2_CFG1
#define PIN_RED__PA__CFG10 CYREG_UDB_PA2_CFG10
#define PIN_RED__PA__CFG11 CYREG_UDB_PA2_CFG11
#define PIN_RED__PA__CFG12 CYREG_UDB_PA2_CFG12
#define PIN_RED__PA__CFG13 CYREG_UDB_PA2_CFG13
#define PIN_RED__PA__CFG14 CYREG_UDB_PA2_CFG14
#define PIN_RED__PA__CFG2 CYREG_UDB_PA2_CFG2
#define PIN_RED__PA__CFG3 CYREG_UDB_PA2_CFG3
#define PIN_RED__PA__CFG4 CYREG_UDB_PA2_CFG4
#define PIN_RED__PA__CFG5 CYREG_UDB_PA2_CFG5
#define PIN_RED__PA__CFG6 CYREG_UDB_PA2_CFG6
#define PIN_RED__PA__CFG7 CYREG_UDB_PA2_CFG7
#define PIN_RED__PA__CFG8 CYREG_UDB_PA2_CFG8
#define PIN_RED__PA__CFG9 CYREG_UDB_PA2_CFG9
#define PIN_RED__PC CYREG_GPIO_PRT2_PC
#define PIN_RED__PC2 CYREG_GPIO_PRT2_PC2
#define PIN_RED__PORT 2u
#define PIN_RED__PS CYREG_GPIO_PRT2_PS
#define PIN_RED__SHIFT 6u

/* PWM_BLUE */
#define PWM_BLUE_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT3_CC
#define PWM_BLUE_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT3_CC_BUFF
#define PWM_BLUE_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT3_COUNTER
#define PWM_BLUE_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT3_CTRL
#define PWM_BLUE_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT3_INTR
#define PWM_BLUE_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT3_INTR_MASK
#define PWM_BLUE_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT3_INTR_MASKED
#define PWM_BLUE_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT3_INTR_SET
#define PWM_BLUE_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT3_PERIOD
#define PWM_BLUE_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT3_PERIOD_BUFF
#define PWM_BLUE_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT3_STATUS
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x08u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 3u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x800u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 11u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x8000000u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 27u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x80000u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 19u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x08u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 3u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x08u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 3u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TCPWM_NUMBER 3u
#define PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT3_TR_CTRL0
#define PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT3_TR_CTRL1
#define PWM_BLUE_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT3_TR_CTRL2

/* PWM_RED */
#define PWM_RED_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT0_CC
#define PWM_RED_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT0_CC_BUFF
#define PWM_RED_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT0_COUNTER
#define PWM_RED_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT0_CTRL
#define PWM_RED_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT0_INTR
#define PWM_RED_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT0_INTR_MASK
#define PWM_RED_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT0_INTR_MASKED
#define PWM_RED_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT0_INTR_SET
#define PWM_RED_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT0_PERIOD
#define PWM_RED_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT0_PERIOD_BUFF
#define PWM_RED_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT0_STATUS
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x01u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 0u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x100u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 8u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x1000000u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 24u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x10000u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 16u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x01u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 0u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x01u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 0u
#define PWM_RED_cy_m0s8_tcpwm_1__TCPWM_NUMBER 0u
#define PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT0_TR_CTRL0
#define PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT0_TR_CTRL1
#define PWM_RED_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT0_TR_CTRL2

/* SENSOR */
#define SENSOR__0__DR CYREG_GPIO_PRT0_DR
#define SENSOR__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define SENSOR__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define SENSOR__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define SENSOR__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define SENSOR__0__HSIOM_MASK 0x00F00000u
#define SENSOR__0__HSIOM_SHIFT 20u
#define SENSOR__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define SENSOR__0__INTR CYREG_GPIO_PRT0_INTR
#define SENSOR__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define SENSOR__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define SENSOR__0__MASK 0x20u
#define SENSOR__0__OUT_SEL CYREG_UDB_PA0_CFG10
#define SENSOR__0__OUT_SEL_SHIFT 10u
#define SENSOR__0__OUT_SEL_VAL 0u
#define SENSOR__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define SENSOR__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define SENSOR__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define SENSOR__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define SENSOR__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define SENSOR__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define SENSOR__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define SENSOR__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define SENSOR__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define SENSOR__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define SENSOR__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define SENSOR__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define SENSOR__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define SENSOR__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define SENSOR__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define SENSOR__0__PC CYREG_GPIO_PRT0_PC
#define SENSOR__0__PC2 CYREG_GPIO_PRT0_PC2
#define SENSOR__0__PORT 0u
#define SENSOR__0__PS CYREG_GPIO_PRT0_PS
#define SENSOR__0__SHIFT 5u
#define SENSOR__1__DR CYREG_GPIO_PRT1_DR
#define SENSOR__1__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define SENSOR__1__DR_INV CYREG_GPIO_PRT1_DR_INV
#define SENSOR__1__DR_SET CYREG_GPIO_PRT1_DR_SET
#define SENSOR__1__HSIOM CYREG_HSIOM_PORT_SEL1
#define SENSOR__1__HSIOM_MASK 0x0000000Fu
#define SENSOR__1__HSIOM_SHIFT 0u
#define SENSOR__1__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__1__INTR CYREG_GPIO_PRT1_INTR
#define SENSOR__1__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__1__INTSTAT CYREG_GPIO_PRT1_INTR
#define SENSOR__1__MASK 0x01u
#define SENSOR__1__OUT_SEL CYREG_UDB_PA1_CFG10
#define SENSOR__1__OUT_SEL_SHIFT 0u
#define SENSOR__1__OUT_SEL_VAL 3u
#define SENSOR__1__PA__CFG0 CYREG_UDB_PA1_CFG0
#define SENSOR__1__PA__CFG1 CYREG_UDB_PA1_CFG1
#define SENSOR__1__PA__CFG10 CYREG_UDB_PA1_CFG10
#define SENSOR__1__PA__CFG11 CYREG_UDB_PA1_CFG11
#define SENSOR__1__PA__CFG12 CYREG_UDB_PA1_CFG12
#define SENSOR__1__PA__CFG13 CYREG_UDB_PA1_CFG13
#define SENSOR__1__PA__CFG14 CYREG_UDB_PA1_CFG14
#define SENSOR__1__PA__CFG2 CYREG_UDB_PA1_CFG2
#define SENSOR__1__PA__CFG3 CYREG_UDB_PA1_CFG3
#define SENSOR__1__PA__CFG4 CYREG_UDB_PA1_CFG4
#define SENSOR__1__PA__CFG5 CYREG_UDB_PA1_CFG5
#define SENSOR__1__PA__CFG6 CYREG_UDB_PA1_CFG6
#define SENSOR__1__PA__CFG7 CYREG_UDB_PA1_CFG7
#define SENSOR__1__PA__CFG8 CYREG_UDB_PA1_CFG8
#define SENSOR__1__PA__CFG9 CYREG_UDB_PA1_CFG9
#define SENSOR__1__PC CYREG_GPIO_PRT1_PC
#define SENSOR__1__PC2 CYREG_GPIO_PRT1_PC2
#define SENSOR__1__PORT 1u
#define SENSOR__1__PS CYREG_GPIO_PRT1_PS
#define SENSOR__1__SHIFT 0u
#define SENSOR__2__DR CYREG_GPIO_PRT1_DR
#define SENSOR__2__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define SENSOR__2__DR_INV CYREG_GPIO_PRT1_DR_INV
#define SENSOR__2__DR_SET CYREG_GPIO_PRT1_DR_SET
#define SENSOR__2__HSIOM CYREG_HSIOM_PORT_SEL1
#define SENSOR__2__HSIOM_MASK 0x000000F0u
#define SENSOR__2__HSIOM_SHIFT 4u
#define SENSOR__2__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__2__INTR CYREG_GPIO_PRT1_INTR
#define SENSOR__2__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__2__INTSTAT CYREG_GPIO_PRT1_INTR
#define SENSOR__2__MASK 0x02u
#define SENSOR__2__OUT_SEL CYREG_UDB_PA1_CFG10
#define SENSOR__2__OUT_SEL_SHIFT 2u
#define SENSOR__2__OUT_SEL_VAL 3u
#define SENSOR__2__PA__CFG0 CYREG_UDB_PA1_CFG0
#define SENSOR__2__PA__CFG1 CYREG_UDB_PA1_CFG1
#define SENSOR__2__PA__CFG10 CYREG_UDB_PA1_CFG10
#define SENSOR__2__PA__CFG11 CYREG_UDB_PA1_CFG11
#define SENSOR__2__PA__CFG12 CYREG_UDB_PA1_CFG12
#define SENSOR__2__PA__CFG13 CYREG_UDB_PA1_CFG13
#define SENSOR__2__PA__CFG14 CYREG_UDB_PA1_CFG14
#define SENSOR__2__PA__CFG2 CYREG_UDB_PA1_CFG2
#define SENSOR__2__PA__CFG3 CYREG_UDB_PA1_CFG3
#define SENSOR__2__PA__CFG4 CYREG_UDB_PA1_CFG4
#define SENSOR__2__PA__CFG5 CYREG_UDB_PA1_CFG5
#define SENSOR__2__PA__CFG6 CYREG_UDB_PA1_CFG6
#define SENSOR__2__PA__CFG7 CYREG_UDB_PA1_CFG7
#define SENSOR__2__PA__CFG8 CYREG_UDB_PA1_CFG8
#define SENSOR__2__PA__CFG9 CYREG_UDB_PA1_CFG9
#define SENSOR__2__PC CYREG_GPIO_PRT1_PC
#define SENSOR__2__PC2 CYREG_GPIO_PRT1_PC2
#define SENSOR__2__PORT 1u
#define SENSOR__2__PS CYREG_GPIO_PRT1_PS
#define SENSOR__2__SHIFT 1u
#define SENSOR__3__DR CYREG_GPIO_PRT1_DR
#define SENSOR__3__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define SENSOR__3__DR_INV CYREG_GPIO_PRT1_DR_INV
#define SENSOR__3__DR_SET CYREG_GPIO_PRT1_DR_SET
#define SENSOR__3__HSIOM CYREG_HSIOM_PORT_SEL1
#define SENSOR__3__HSIOM_MASK 0x00000F00u
#define SENSOR__3__HSIOM_SHIFT 8u
#define SENSOR__3__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__3__INTR CYREG_GPIO_PRT1_INTR
#define SENSOR__3__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__3__INTSTAT CYREG_GPIO_PRT1_INTR
#define SENSOR__3__MASK 0x04u
#define SENSOR__3__OUT_SEL CYREG_UDB_PA1_CFG10
#define SENSOR__3__OUT_SEL_SHIFT 4u
#define SENSOR__3__OUT_SEL_VAL 3u
#define SENSOR__3__PA__CFG0 CYREG_UDB_PA1_CFG0
#define SENSOR__3__PA__CFG1 CYREG_UDB_PA1_CFG1
#define SENSOR__3__PA__CFG10 CYREG_UDB_PA1_CFG10
#define SENSOR__3__PA__CFG11 CYREG_UDB_PA1_CFG11
#define SENSOR__3__PA__CFG12 CYREG_UDB_PA1_CFG12
#define SENSOR__3__PA__CFG13 CYREG_UDB_PA1_CFG13
#define SENSOR__3__PA__CFG14 CYREG_UDB_PA1_CFG14
#define SENSOR__3__PA__CFG2 CYREG_UDB_PA1_CFG2
#define SENSOR__3__PA__CFG3 CYREG_UDB_PA1_CFG3
#define SENSOR__3__PA__CFG4 CYREG_UDB_PA1_CFG4
#define SENSOR__3__PA__CFG5 CYREG_UDB_PA1_CFG5
#define SENSOR__3__PA__CFG6 CYREG_UDB_PA1_CFG6
#define SENSOR__3__PA__CFG7 CYREG_UDB_PA1_CFG7
#define SENSOR__3__PA__CFG8 CYREG_UDB_PA1_CFG8
#define SENSOR__3__PA__CFG9 CYREG_UDB_PA1_CFG9
#define SENSOR__3__PC CYREG_GPIO_PRT1_PC
#define SENSOR__3__PC2 CYREG_GPIO_PRT1_PC2
#define SENSOR__3__PORT 1u
#define SENSOR__3__PS CYREG_GPIO_PRT1_PS
#define SENSOR__3__SHIFT 2u
#define SENSOR__4__DR CYREG_GPIO_PRT1_DR
#define SENSOR__4__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define SENSOR__4__DR_INV CYREG_GPIO_PRT1_DR_INV
#define SENSOR__4__DR_SET CYREG_GPIO_PRT1_DR_SET
#define SENSOR__4__HSIOM CYREG_HSIOM_PORT_SEL1
#define SENSOR__4__HSIOM_MASK 0x0000F000u
#define SENSOR__4__HSIOM_SHIFT 12u
#define SENSOR__4__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__4__INTR CYREG_GPIO_PRT1_INTR
#define SENSOR__4__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__4__INTSTAT CYREG_GPIO_PRT1_INTR
#define SENSOR__4__MASK 0x08u
#define SENSOR__4__OUT_SEL CYREG_UDB_PA1_CFG11
#define SENSOR__4__OUT_SEL_SHIFT 6u
#define SENSOR__4__OUT_SEL_VAL 3u
#define SENSOR__4__PA__CFG0 CYREG_UDB_PA1_CFG0
#define SENSOR__4__PA__CFG1 CYREG_UDB_PA1_CFG1
#define SENSOR__4__PA__CFG10 CYREG_UDB_PA1_CFG10
#define SENSOR__4__PA__CFG11 CYREG_UDB_PA1_CFG11
#define SENSOR__4__PA__CFG12 CYREG_UDB_PA1_CFG12
#define SENSOR__4__PA__CFG13 CYREG_UDB_PA1_CFG13
#define SENSOR__4__PA__CFG14 CYREG_UDB_PA1_CFG14
#define SENSOR__4__PA__CFG2 CYREG_UDB_PA1_CFG2
#define SENSOR__4__PA__CFG3 CYREG_UDB_PA1_CFG3
#define SENSOR__4__PA__CFG4 CYREG_UDB_PA1_CFG4
#define SENSOR__4__PA__CFG5 CYREG_UDB_PA1_CFG5
#define SENSOR__4__PA__CFG6 CYREG_UDB_PA1_CFG6
#define SENSOR__4__PA__CFG7 CYREG_UDB_PA1_CFG7
#define SENSOR__4__PA__CFG8 CYREG_UDB_PA1_CFG8
#define SENSOR__4__PA__CFG9 CYREG_UDB_PA1_CFG9
#define SENSOR__4__PC CYREG_GPIO_PRT1_PC
#define SENSOR__4__PC2 CYREG_GPIO_PRT1_PC2
#define SENSOR__4__PORT 1u
#define SENSOR__4__PS CYREG_GPIO_PRT1_PS
#define SENSOR__4__SHIFT 3u
#define SENSOR__5__DR CYREG_GPIO_PRT1_DR
#define SENSOR__5__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define SENSOR__5__DR_INV CYREG_GPIO_PRT1_DR_INV
#define SENSOR__5__DR_SET CYREG_GPIO_PRT1_DR_SET
#define SENSOR__5__HSIOM CYREG_HSIOM_PORT_SEL1
#define SENSOR__5__HSIOM_MASK 0x0F000000u
#define SENSOR__5__HSIOM_SHIFT 24u
#define SENSOR__5__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__5__INTR CYREG_GPIO_PRT1_INTR
#define SENSOR__5__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__5__INTSTAT CYREG_GPIO_PRT1_INTR
#define SENSOR__5__MASK 0x40u
#define SENSOR__5__OUT_SEL CYREG_UDB_PA1_CFG11
#define SENSOR__5__OUT_SEL_SHIFT 12u
#define SENSOR__5__OUT_SEL_VAL 0u
#define SENSOR__5__PA__CFG0 CYREG_UDB_PA1_CFG0
#define SENSOR__5__PA__CFG1 CYREG_UDB_PA1_CFG1
#define SENSOR__5__PA__CFG10 CYREG_UDB_PA1_CFG10
#define SENSOR__5__PA__CFG11 CYREG_UDB_PA1_CFG11
#define SENSOR__5__PA__CFG12 CYREG_UDB_PA1_CFG12
#define SENSOR__5__PA__CFG13 CYREG_UDB_PA1_CFG13
#define SENSOR__5__PA__CFG14 CYREG_UDB_PA1_CFG14
#define SENSOR__5__PA__CFG2 CYREG_UDB_PA1_CFG2
#define SENSOR__5__PA__CFG3 CYREG_UDB_PA1_CFG3
#define SENSOR__5__PA__CFG4 CYREG_UDB_PA1_CFG4
#define SENSOR__5__PA__CFG5 CYREG_UDB_PA1_CFG5
#define SENSOR__5__PA__CFG6 CYREG_UDB_PA1_CFG6
#define SENSOR__5__PA__CFG7 CYREG_UDB_PA1_CFG7
#define SENSOR__5__PA__CFG8 CYREG_UDB_PA1_CFG8
#define SENSOR__5__PA__CFG9 CYREG_UDB_PA1_CFG9
#define SENSOR__5__PC CYREG_GPIO_PRT1_PC
#define SENSOR__5__PC2 CYREG_GPIO_PRT1_PC2
#define SENSOR__5__PORT 1u
#define SENSOR__5__PS CYREG_GPIO_PRT1_PS
#define SENSOR__5__SHIFT 6u
#define SENSOR__6__DR CYREG_GPIO_PRT1_DR
#define SENSOR__6__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define SENSOR__6__DR_INV CYREG_GPIO_PRT1_DR_INV
#define SENSOR__6__DR_SET CYREG_GPIO_PRT1_DR_SET
#define SENSOR__6__HSIOM CYREG_HSIOM_PORT_SEL1
#define SENSOR__6__HSIOM_MASK 0xF0000000u
#define SENSOR__6__HSIOM_SHIFT 28u
#define SENSOR__6__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__6__INTR CYREG_GPIO_PRT1_INTR
#define SENSOR__6__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define SENSOR__6__INTSTAT CYREG_GPIO_PRT1_INTR
#define SENSOR__6__MASK 0x80u
#define SENSOR__6__OUT_SEL CYREG_UDB_PA1_CFG11
#define SENSOR__6__OUT_SEL_SHIFT 14u
#define SENSOR__6__OUT_SEL_VAL 0u
#define SENSOR__6__PA__CFG0 CYREG_UDB_PA1_CFG0
#define SENSOR__6__PA__CFG1 CYREG_UDB_PA1_CFG1
#define SENSOR__6__PA__CFG10 CYREG_UDB_PA1_CFG10
#define SENSOR__6__PA__CFG11 CYREG_UDB_PA1_CFG11
#define SENSOR__6__PA__CFG12 CYREG_UDB_PA1_CFG12
#define SENSOR__6__PA__CFG13 CYREG_UDB_PA1_CFG13
#define SENSOR__6__PA__CFG14 CYREG_UDB_PA1_CFG14
#define SENSOR__6__PA__CFG2 CYREG_UDB_PA1_CFG2
#define SENSOR__6__PA__CFG3 CYREG_UDB_PA1_CFG3
#define SENSOR__6__PA__CFG4 CYREG_UDB_PA1_CFG4
#define SENSOR__6__PA__CFG5 CYREG_UDB_PA1_CFG5
#define SENSOR__6__PA__CFG6 CYREG_UDB_PA1_CFG6
#define SENSOR__6__PA__CFG7 CYREG_UDB_PA1_CFG7
#define SENSOR__6__PA__CFG8 CYREG_UDB_PA1_CFG8
#define SENSOR__6__PA__CFG9 CYREG_UDB_PA1_CFG9
#define SENSOR__6__PC CYREG_GPIO_PRT1_PC
#define SENSOR__6__PC2 CYREG_GPIO_PRT1_PC2
#define SENSOR__6__PORT 1u
#define SENSOR__6__PS CYREG_GPIO_PRT1_PS
#define SENSOR__6__SHIFT 7u
#define SENSOR__7__DR CYREG_GPIO_PRT2_DR
#define SENSOR__7__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SENSOR__7__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SENSOR__7__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SENSOR__7__HSIOM CYREG_HSIOM_PORT_SEL2
#define SENSOR__7__HSIOM_MASK 0x0000000Fu
#define SENSOR__7__HSIOM_SHIFT 0u
#define SENSOR__7__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SENSOR__7__INTR CYREG_GPIO_PRT2_INTR
#define SENSOR__7__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SENSOR__7__INTSTAT CYREG_GPIO_PRT2_INTR
#define SENSOR__7__MASK 0x01u
#define SENSOR__7__OUT_SEL CYREG_UDB_PA2_CFG11
#define SENSOR__7__OUT_SEL_SHIFT 0u
#define SENSOR__7__OUT_SEL_VAL 1u
#define SENSOR__7__PA__CFG0 CYREG_UDB_PA2_CFG0
#define SENSOR__7__PA__CFG1 CYREG_UDB_PA2_CFG1
#define SENSOR__7__PA__CFG10 CYREG_UDB_PA2_CFG10
#define SENSOR__7__PA__CFG11 CYREG_UDB_PA2_CFG11
#define SENSOR__7__PA__CFG12 CYREG_UDB_PA2_CFG12
#define SENSOR__7__PA__CFG13 CYREG_UDB_PA2_CFG13
#define SENSOR__7__PA__CFG14 CYREG_UDB_PA2_CFG14
#define SENSOR__7__PA__CFG2 CYREG_UDB_PA2_CFG2
#define SENSOR__7__PA__CFG3 CYREG_UDB_PA2_CFG3
#define SENSOR__7__PA__CFG4 CYREG_UDB_PA2_CFG4
#define SENSOR__7__PA__CFG5 CYREG_UDB_PA2_CFG5
#define SENSOR__7__PA__CFG6 CYREG_UDB_PA2_CFG6
#define SENSOR__7__PA__CFG7 CYREG_UDB_PA2_CFG7
#define SENSOR__7__PA__CFG8 CYREG_UDB_PA2_CFG8
#define SENSOR__7__PA__CFG9 CYREG_UDB_PA2_CFG9
#define SENSOR__7__PC CYREG_GPIO_PRT2_PC
#define SENSOR__7__PC2 CYREG_GPIO_PRT2_PC2
#define SENSOR__7__PORT 2u
#define SENSOR__7__PS CYREG_GPIO_PRT2_PS
#define SENSOR__7__SHIFT 0u
#define SENSOR__8__DR CYREG_GPIO_PRT2_DR
#define SENSOR__8__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SENSOR__8__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SENSOR__8__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SENSOR__8__HSIOM CYREG_HSIOM_PORT_SEL2
#define SENSOR__8__HSIOM_MASK 0x000000F0u
#define SENSOR__8__HSIOM_SHIFT 4u
#define SENSOR__8__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SENSOR__8__INTR CYREG_GPIO_PRT2_INTR
#define SENSOR__8__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SENSOR__8__INTSTAT CYREG_GPIO_PRT2_INTR
#define SENSOR__8__MASK 0x02u
#define SENSOR__8__OUT_SEL CYREG_UDB_PA2_CFG11
#define SENSOR__8__OUT_SEL_SHIFT 2u
#define SENSOR__8__OUT_SEL_VAL 1u
#define SENSOR__8__PA__CFG0 CYREG_UDB_PA2_CFG0
#define SENSOR__8__PA__CFG1 CYREG_UDB_PA2_CFG1
#define SENSOR__8__PA__CFG10 CYREG_UDB_PA2_CFG10
#define SENSOR__8__PA__CFG11 CYREG_UDB_PA2_CFG11
#define SENSOR__8__PA__CFG12 CYREG_UDB_PA2_CFG12
#define SENSOR__8__PA__CFG13 CYREG_UDB_PA2_CFG13
#define SENSOR__8__PA__CFG14 CYREG_UDB_PA2_CFG14
#define SENSOR__8__PA__CFG2 CYREG_UDB_PA2_CFG2
#define SENSOR__8__PA__CFG3 CYREG_UDB_PA2_CFG3
#define SENSOR__8__PA__CFG4 CYREG_UDB_PA2_CFG4
#define SENSOR__8__PA__CFG5 CYREG_UDB_PA2_CFG5
#define SENSOR__8__PA__CFG6 CYREG_UDB_PA2_CFG6
#define SENSOR__8__PA__CFG7 CYREG_UDB_PA2_CFG7
#define SENSOR__8__PA__CFG8 CYREG_UDB_PA2_CFG8
#define SENSOR__8__PA__CFG9 CYREG_UDB_PA2_CFG9
#define SENSOR__8__PC CYREG_GPIO_PRT2_PC
#define SENSOR__8__PC2 CYREG_GPIO_PRT2_PC2
#define SENSOR__8__PORT 2u
#define SENSOR__8__PS CYREG_GPIO_PRT2_PS
#define SENSOR__8__SHIFT 1u

/* SW */
#define SW__0__DR CYREG_GPIO_PRT2_DR
#define SW__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SW__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SW__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SW__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define SW__0__HSIOM_MASK 0xF0000000u
#define SW__0__HSIOM_SHIFT 28u
#define SW__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SW__0__INTR CYREG_GPIO_PRT2_INTR
#define SW__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SW__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define SW__0__MASK 0x80u
#define SW__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define SW__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define SW__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define SW__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define SW__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define SW__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define SW__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define SW__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define SW__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define SW__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define SW__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define SW__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define SW__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define SW__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define SW__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define SW__0__PC CYREG_GPIO_PRT2_PC
#define SW__0__PC2 CYREG_GPIO_PRT2_PC2
#define SW__0__PORT 2u
#define SW__0__PS CYREG_GPIO_PRT2_PS
#define SW__0__SHIFT 7u
#define SW__DR CYREG_GPIO_PRT2_DR
#define SW__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define SW__DR_INV CYREG_GPIO_PRT2_DR_INV
#define SW__DR_SET CYREG_GPIO_PRT2_DR_SET
#define SW__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define SW__INTR CYREG_GPIO_PRT2_INTR
#define SW__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define SW__INTSTAT CYREG_GPIO_PRT2_INTR
#define SW__MASK 0x80u
#define SW__PA__CFG0 CYREG_UDB_PA2_CFG0
#define SW__PA__CFG1 CYREG_UDB_PA2_CFG1
#define SW__PA__CFG10 CYREG_UDB_PA2_CFG10
#define SW__PA__CFG11 CYREG_UDB_PA2_CFG11
#define SW__PA__CFG12 CYREG_UDB_PA2_CFG12
#define SW__PA__CFG13 CYREG_UDB_PA2_CFG13
#define SW__PA__CFG14 CYREG_UDB_PA2_CFG14
#define SW__PA__CFG2 CYREG_UDB_PA2_CFG2
#define SW__PA__CFG3 CYREG_UDB_PA2_CFG3
#define SW__PA__CFG4 CYREG_UDB_PA2_CFG4
#define SW__PA__CFG5 CYREG_UDB_PA2_CFG5
#define SW__PA__CFG6 CYREG_UDB_PA2_CFG6
#define SW__PA__CFG7 CYREG_UDB_PA2_CFG7
#define SW__PA__CFG8 CYREG_UDB_PA2_CFG8
#define SW__PA__CFG9 CYREG_UDB_PA2_CFG9
#define SW__PC CYREG_GPIO_PRT2_PC
#define SW__PC2 CYREG_GPIO_PRT2_PC2
#define SW__PORT 2u
#define SW__PS CYREG_GPIO_PRT2_PS
#define SW__SHIFT 7u

/* SwClk */
#define SwClk__CTRL_REGISTER CYREG_PERI_PCLK_CTL11
#define SwClk__DIV_ID 0x00000042u
#define SwClk__DIV_REGISTER CYREG_PERI_DIV_16_CTL2
#define SwClk__PA_DIV_ID 0x000000FFu

/* TC_ISR */
#define TC_ISR__INTC_CLR_EN_REG CYREG_CM0_ICER
#define TC_ISR__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define TC_ISR__INTC_MASK 0x100000u
#define TC_ISR__INTC_NUMBER 20u
#define TC_ISR__INTC_PRIOR_MASK 0xC0u
#define TC_ISR__INTC_PRIOR_NUM 3u
#define TC_ISR__INTC_PRIOR_REG CYREG_CM0_IPR5
#define TC_ISR__INTC_SET_EN_REG CYREG_CM0_ISER
#define TC_ISR__INTC_SET_PD_REG CYREG_CM0_ISPR
#define TC_ISR_1__INTC_CLR_EN_REG CYREG_CM0_ICER
#define TC_ISR_1__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define TC_ISR_1__INTC_MASK 0x20000u
#define TC_ISR_1__INTC_NUMBER 17u
#define TC_ISR_1__INTC_PRIOR_MASK 0xC000u
#define TC_ISR_1__INTC_PRIOR_NUM 3u
#define TC_ISR_1__INTC_PRIOR_REG CYREG_CM0_IPR4
#define TC_ISR_1__INTC_SET_EN_REG CYREG_CM0_ISER
#define TC_ISR_1__INTC_SET_PD_REG CYREG_CM0_ISPR

/* Timer_1_TimerUDB */
#define Timer_1_TimerUDB_rstSts_stsreg__0__MASK 0x01u
#define Timer_1_TimerUDB_rstSts_stsreg__0__POS 0
#define Timer_1_TimerUDB_rstSts_stsreg__2__MASK 0x04u
#define Timer_1_TimerUDB_rstSts_stsreg__2__POS 2
#define Timer_1_TimerUDB_rstSts_stsreg__3__MASK 0x08u
#define Timer_1_TimerUDB_rstSts_stsreg__3__POS 3
#define Timer_1_TimerUDB_rstSts_stsreg__MASK 0x0Du
#define Timer_1_TimerUDB_rstSts_stsreg__MASK_REG CYREG_UDB_W8_MSK3
#define Timer_1_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG CYREG_UDB_W8_ACTL3
#define Timer_1_TimerUDB_rstSts_stsreg__STATUS_REG CYREG_UDB_W8_ST3
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_AUX_CTL_REG CYREG_UDB_W16_ACTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_CONTROL_REG CYREG_UDB_W16_CTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_CONTROL_COUNT_REG CYREG_UDB_W16_CTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_CONTROL_REG CYREG_UDB_W16_CTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_COUNT_COUNT_REG CYREG_UDB_W16_CTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_MASK_REG CYREG_UDB_W16_MSK0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_MASK_PERIOD_REG CYREG_UDB_W16_MSK0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_MASK_REG CYREG_UDB_W16_MSK0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__16BIT_PERIOD_PERIOD_REG CYREG_UDB_W16_MSK0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_CONTROL_AUX_CTL_REG CYREG_UDB_W32_ACTL
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_CONTROL_REG CYREG_UDB_W32_CTL
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_COUNT_REG CYREG_UDB_W32_CTL
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__32BIT_PERIOD_REG CYREG_UDB_W32_MSK
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__MASK 0x80u
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__7__POS 7
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_AUX_CTL_REG CYREG_UDB_W8_ACTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG CYREG_UDB_W8_CTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_ST_REG CYREG_UDB_CAT16_CTL_ST0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_REG CYREG_UDB_W8_CTL0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__COUNT_ST_REG CYREG_UDB_CAT16_CTL_ST0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK 0x80u
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__MASK_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PER_CTL_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK0
#define Timer_1_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__PERIOD_REG CYREG_UDB_W8_MSK0
#define Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_A0_REG CYREG_UDB_W16_A00
#define Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_A1_REG CYREG_UDB_W16_A10
#define Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_D0_REG CYREG_UDB_W16_D00
#define Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_D1_REG CYREG_UDB_W16_D10
#define Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_DP_AUX_CTL_REG CYREG_UDB_W16_ACTL0
#define Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_F0_REG CYREG_UDB_W16_F00
#define Timer_1_TimerUDB_sT32_timerdp_u0__16BIT_F1_REG CYREG_UDB_W16_F10
#define Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_A0_REG CYREG_UDB_W32_A0
#define Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_A1_REG CYREG_UDB_W32_A1
#define Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_D0_REG CYREG_UDB_W32_D0
#define Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_D1_REG CYREG_UDB_W32_D1
#define Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_DP_AUX_CTL_REG CYREG_UDB_W32_ACTL
#define Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_F0_REG CYREG_UDB_W32_F0
#define Timer_1_TimerUDB_sT32_timerdp_u0__32BIT_F1_REG CYREG_UDB_W32_F1
#define Timer_1_TimerUDB_sT32_timerdp_u0__A0_A1_REG CYREG_UDB_CAT16_A0
#define Timer_1_TimerUDB_sT32_timerdp_u0__A0_REG CYREG_UDB_W8_A00
#define Timer_1_TimerUDB_sT32_timerdp_u0__A1_REG CYREG_UDB_W8_A10
#define Timer_1_TimerUDB_sT32_timerdp_u0__D0_D1_REG CYREG_UDB_CAT16_D0
#define Timer_1_TimerUDB_sT32_timerdp_u0__D0_REG CYREG_UDB_W8_D00
#define Timer_1_TimerUDB_sT32_timerdp_u0__D1_REG CYREG_UDB_W8_D10
#define Timer_1_TimerUDB_sT32_timerdp_u0__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL0
#define Timer_1_TimerUDB_sT32_timerdp_u0__F0_F1_REG CYREG_UDB_CAT16_F0
#define Timer_1_TimerUDB_sT32_timerdp_u0__F0_REG CYREG_UDB_W8_F00
#define Timer_1_TimerUDB_sT32_timerdp_u0__F1_REG CYREG_UDB_W8_F10
#define Timer_1_TimerUDB_sT32_timerdp_u0__MSK_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK0
#define Timer_1_TimerUDB_sT32_timerdp_u0__PER_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK0
#define Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_A0_REG CYREG_UDB_W16_A01
#define Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_A1_REG CYREG_UDB_W16_A11
#define Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_D0_REG CYREG_UDB_W16_D01
#define Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_D1_REG CYREG_UDB_W16_D11
#define Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_DP_AUX_CTL_REG CYREG_UDB_W16_ACTL1
#define Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_F0_REG CYREG_UDB_W16_F01
#define Timer_1_TimerUDB_sT32_timerdp_u1__16BIT_F1_REG CYREG_UDB_W16_F11
#define Timer_1_TimerUDB_sT32_timerdp_u1__A0_A1_REG CYREG_UDB_CAT16_A1
#define Timer_1_TimerUDB_sT32_timerdp_u1__A0_REG CYREG_UDB_W8_A01
#define Timer_1_TimerUDB_sT32_timerdp_u1__A1_REG CYREG_UDB_W8_A11
#define Timer_1_TimerUDB_sT32_timerdp_u1__D0_D1_REG CYREG_UDB_CAT16_D1
#define Timer_1_TimerUDB_sT32_timerdp_u1__D0_REG CYREG_UDB_W8_D01
#define Timer_1_TimerUDB_sT32_timerdp_u1__D1_REG CYREG_UDB_W8_D11
#define Timer_1_TimerUDB_sT32_timerdp_u1__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL1
#define Timer_1_TimerUDB_sT32_timerdp_u1__F0_F1_REG CYREG_UDB_CAT16_F1
#define Timer_1_TimerUDB_sT32_timerdp_u1__F0_REG CYREG_UDB_W8_F01
#define Timer_1_TimerUDB_sT32_timerdp_u1__F1_REG CYREG_UDB_W8_F11
#define Timer_1_TimerUDB_sT32_timerdp_u1__MSK_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK1
#define Timer_1_TimerUDB_sT32_timerdp_u1__PER_DP_AUX_CTL_REG CYREG_UDB_CAT16_ACTL_MSK1
#define Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_A0_REG CYREG_UDB_W16_A02
#define Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_A1_REG CYREG_UDB_W16_A12
#define Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_D0_REG CYREG_UDB_W16_D02
#define Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_D1_REG CYREG_UDB_W16_D12
#define Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_DP_AUX_CTL_REG CYREG_UDB_W16_ACTL2
#define Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_F0_REG CYREG_UDB_W16_F02
#define Timer_1_TimerUDB_sT32_timerdp_u2__16BIT_F1_REG CYREG_UDB_W16_F12
#define Timer_1_TimerUDB_sT32_timerdp_u2__A0_A1_REG CYREG_UDB_CAT16_A2
#define Timer_1_TimerUDB_sT32_timerdp_u2__A0_REG CYREG_UDB_W8_A02
#define Timer_1_TimerUDB_sT32_timerdp_u2__A1_REG CYREG_UDB_W8_A12
#define Timer_1_TimerUDB_sT32_timerdp_u2__D0_D1_REG CYREG_UDB_CAT16_D2
#define Timer_1_TimerUDB_sT32_timerdp_u2__D0_REG CYREG_UDB_W8_D02
#define Timer_1_TimerUDB_sT32_timerdp_u2__D1_REG CYREG_UDB_W8_D12
#define Timer_1_TimerUDB_sT32_timerdp_u2__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL2
#define Timer_1_TimerUDB_sT32_timerdp_u2__F0_F1_REG CYREG_UDB_CAT16_F2
#define Timer_1_TimerUDB_sT32_timerdp_u2__F0_REG CYREG_UDB_W8_F02
#define Timer_1_TimerUDB_sT32_timerdp_u2__F1_REG CYREG_UDB_W8_F12
#define Timer_1_TimerUDB_sT32_timerdp_u3__A0_A1_REG CYREG_UDB_CAT16_A3
#define Timer_1_TimerUDB_sT32_timerdp_u3__A0_REG CYREG_UDB_W8_A03
#define Timer_1_TimerUDB_sT32_timerdp_u3__A1_REG CYREG_UDB_W8_A13
#define Timer_1_TimerUDB_sT32_timerdp_u3__D0_D1_REG CYREG_UDB_CAT16_D3
#define Timer_1_TimerUDB_sT32_timerdp_u3__D0_REG CYREG_UDB_W8_D03
#define Timer_1_TimerUDB_sT32_timerdp_u3__D1_REG CYREG_UDB_W8_D13
#define Timer_1_TimerUDB_sT32_timerdp_u3__DP_AUX_CTL_REG CYREG_UDB_W8_ACTL3
#define Timer_1_TimerUDB_sT32_timerdp_u3__F0_F1_REG CYREG_UDB_CAT16_F3
#define Timer_1_TimerUDB_sT32_timerdp_u3__F0_REG CYREG_UDB_W8_F03
#define Timer_1_TimerUDB_sT32_timerdp_u3__F1_REG CYREG_UDB_W8_F13

/* UART */
#define UART_rx__0__DR CYREG_GPIO_PRT1_DR
#define UART_rx__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_rx__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_rx__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_rx__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define UART_rx__0__HSIOM_GPIO 0u
#define UART_rx__0__HSIOM_I2C 14u
#define UART_rx__0__HSIOM_I2C_SDA 14u
#define UART_rx__0__HSIOM_MASK 0x000F0000u
#define UART_rx__0__HSIOM_SHIFT 16u
#define UART_rx__0__HSIOM_SPI 15u
#define UART_rx__0__HSIOM_SPI_MOSI 15u
#define UART_rx__0__HSIOM_UART 9u
#define UART_rx__0__HSIOM_UART_RX 9u
#define UART_rx__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__0__INTR CYREG_GPIO_PRT1_INTR
#define UART_rx__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_rx__0__MASK 0x10u
#define UART_rx__0__PA__CFG0 CYREG_UDB_PA1_CFG0
#define UART_rx__0__PA__CFG1 CYREG_UDB_PA1_CFG1
#define UART_rx__0__PA__CFG10 CYREG_UDB_PA1_CFG10
#define UART_rx__0__PA__CFG11 CYREG_UDB_PA1_CFG11
#define UART_rx__0__PA__CFG12 CYREG_UDB_PA1_CFG12
#define UART_rx__0__PA__CFG13 CYREG_UDB_PA1_CFG13
#define UART_rx__0__PA__CFG14 CYREG_UDB_PA1_CFG14
#define UART_rx__0__PA__CFG2 CYREG_UDB_PA1_CFG2
#define UART_rx__0__PA__CFG3 CYREG_UDB_PA1_CFG3
#define UART_rx__0__PA__CFG4 CYREG_UDB_PA1_CFG4
#define UART_rx__0__PA__CFG5 CYREG_UDB_PA1_CFG5
#define UART_rx__0__PA__CFG6 CYREG_UDB_PA1_CFG6
#define UART_rx__0__PA__CFG7 CYREG_UDB_PA1_CFG7
#define UART_rx__0__PA__CFG8 CYREG_UDB_PA1_CFG8
#define UART_rx__0__PA__CFG9 CYREG_UDB_PA1_CFG9
#define UART_rx__0__PC CYREG_GPIO_PRT1_PC
#define UART_rx__0__PC2 CYREG_GPIO_PRT1_PC2
#define UART_rx__0__PORT 1u
#define UART_rx__0__PS CYREG_GPIO_PRT1_PS
#define UART_rx__0__SHIFT 4u
#define UART_rx__DR CYREG_GPIO_PRT1_DR
#define UART_rx__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_rx__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_rx__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_rx__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__INTR CYREG_GPIO_PRT1_INTR
#define UART_rx__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_rx__MASK 0x10u
#define UART_rx__PA__CFG0 CYREG_UDB_PA1_CFG0
#define UART_rx__PA__CFG1 CYREG_UDB_PA1_CFG1
#define UART_rx__PA__CFG10 CYREG_UDB_PA1_CFG10
#define UART_rx__PA__CFG11 CYREG_UDB_PA1_CFG11
#define UART_rx__PA__CFG12 CYREG_UDB_PA1_CFG12
#define UART_rx__PA__CFG13 CYREG_UDB_PA1_CFG13
#define UART_rx__PA__CFG14 CYREG_UDB_PA1_CFG14
#define UART_rx__PA__CFG2 CYREG_UDB_PA1_CFG2
#define UART_rx__PA__CFG3 CYREG_UDB_PA1_CFG3
#define UART_rx__PA__CFG4 CYREG_UDB_PA1_CFG4
#define UART_rx__PA__CFG5 CYREG_UDB_PA1_CFG5
#define UART_rx__PA__CFG6 CYREG_UDB_PA1_CFG6
#define UART_rx__PA__CFG7 CYREG_UDB_PA1_CFG7
#define UART_rx__PA__CFG8 CYREG_UDB_PA1_CFG8
#define UART_rx__PA__CFG9 CYREG_UDB_PA1_CFG9
#define UART_rx__PC CYREG_GPIO_PRT1_PC
#define UART_rx__PC2 CYREG_GPIO_PRT1_PC2
#define UART_rx__PORT 1u
#define UART_rx__PS CYREG_GPIO_PRT1_PS
#define UART_rx__SHIFT 4u
#define UART_SCB__CTRL CYREG_SCB0_CTRL
#define UART_SCB__EZ_DATA0 CYREG_SCB0_EZ_DATA0
#define UART_SCB__EZ_DATA1 CYREG_SCB0_EZ_DATA1
#define UART_SCB__EZ_DATA10 CYREG_SCB0_EZ_DATA10
#define UART_SCB__EZ_DATA11 CYREG_SCB0_EZ_DATA11
#define UART_SCB__EZ_DATA12 CYREG_SCB0_EZ_DATA12
#define UART_SCB__EZ_DATA13 CYREG_SCB0_EZ_DATA13
#define UART_SCB__EZ_DATA14 CYREG_SCB0_EZ_DATA14
#define UART_SCB__EZ_DATA15 CYREG_SCB0_EZ_DATA15
#define UART_SCB__EZ_DATA16 CYREG_SCB0_EZ_DATA16
#define UART_SCB__EZ_DATA17 CYREG_SCB0_EZ_DATA17
#define UART_SCB__EZ_DATA18 CYREG_SCB0_EZ_DATA18
#define UART_SCB__EZ_DATA19 CYREG_SCB0_EZ_DATA19
#define UART_SCB__EZ_DATA2 CYREG_SCB0_EZ_DATA2
#define UART_SCB__EZ_DATA20 CYREG_SCB0_EZ_DATA20
#define UART_SCB__EZ_DATA21 CYREG_SCB0_EZ_DATA21
#define UART_SCB__EZ_DATA22 CYREG_SCB0_EZ_DATA22
#define UART_SCB__EZ_DATA23 CYREG_SCB0_EZ_DATA23
#define UART_SCB__EZ_DATA24 CYREG_SCB0_EZ_DATA24
#define UART_SCB__EZ_DATA25 CYREG_SCB0_EZ_DATA25
#define UART_SCB__EZ_DATA26 CYREG_SCB0_EZ_DATA26
#define UART_SCB__EZ_DATA27 CYREG_SCB0_EZ_DATA27
#define UART_SCB__EZ_DATA28 CYREG_SCB0_EZ_DATA28
#define UART_SCB__EZ_DATA29 CYREG_SCB0_EZ_DATA29
#define UART_SCB__EZ_DATA3 CYREG_SCB0_EZ_DATA3
#define UART_SCB__EZ_DATA30 CYREG_SCB0_EZ_DATA30
#define UART_SCB__EZ_DATA31 CYREG_SCB0_EZ_DATA31
#define UART_SCB__EZ_DATA4 CYREG_SCB0_EZ_DATA4
#define UART_SCB__EZ_DATA5 CYREG_SCB0_EZ_DATA5
#define UART_SCB__EZ_DATA6 CYREG_SCB0_EZ_DATA6
#define UART_SCB__EZ_DATA7 CYREG_SCB0_EZ_DATA7
#define UART_SCB__EZ_DATA8 CYREG_SCB0_EZ_DATA8
#define UART_SCB__EZ_DATA9 CYREG_SCB0_EZ_DATA9
#define UART_SCB__I2C_CFG CYREG_SCB0_I2C_CFG
#define UART_SCB__I2C_CTRL CYREG_SCB0_I2C_CTRL
#define UART_SCB__I2C_M_CMD CYREG_SCB0_I2C_M_CMD
#define UART_SCB__I2C_S_CMD CYREG_SCB0_I2C_S_CMD
#define UART_SCB__I2C_STATUS CYREG_SCB0_I2C_STATUS
#define UART_SCB__INTR_CAUSE CYREG_SCB0_INTR_CAUSE
#define UART_SCB__INTR_I2C_EC CYREG_SCB0_INTR_I2C_EC
#define UART_SCB__INTR_I2C_EC_MASK CYREG_SCB0_INTR_I2C_EC_MASK
#define UART_SCB__INTR_I2C_EC_MASKED CYREG_SCB0_INTR_I2C_EC_MASKED
#define UART_SCB__INTR_M CYREG_SCB0_INTR_M
#define UART_SCB__INTR_M_MASK CYREG_SCB0_INTR_M_MASK
#define UART_SCB__INTR_M_MASKED CYREG_SCB0_INTR_M_MASKED
#define UART_SCB__INTR_M_SET CYREG_SCB0_INTR_M_SET
#define UART_SCB__INTR_RX CYREG_SCB0_INTR_RX
#define UART_SCB__INTR_RX_MASK CYREG_SCB0_INTR_RX_MASK
#define UART_SCB__INTR_RX_MASKED CYREG_SCB0_INTR_RX_MASKED
#define UART_SCB__INTR_RX_SET CYREG_SCB0_INTR_RX_SET
#define UART_SCB__INTR_S CYREG_SCB0_INTR_S
#define UART_SCB__INTR_S_MASK CYREG_SCB0_INTR_S_MASK
#define UART_SCB__INTR_S_MASKED CYREG_SCB0_INTR_S_MASKED
#define UART_SCB__INTR_S_SET CYREG_SCB0_INTR_S_SET
#define UART_SCB__INTR_SPI_EC CYREG_SCB0_INTR_SPI_EC
#define UART_SCB__INTR_SPI_EC_MASK CYREG_SCB0_INTR_SPI_EC_MASK
#define UART_SCB__INTR_SPI_EC_MASKED CYREG_SCB0_INTR_SPI_EC_MASKED
#define UART_SCB__INTR_TX CYREG_SCB0_INTR_TX
#define UART_SCB__INTR_TX_MASK CYREG_SCB0_INTR_TX_MASK
#define UART_SCB__INTR_TX_MASKED CYREG_SCB0_INTR_TX_MASKED
#define UART_SCB__INTR_TX_SET CYREG_SCB0_INTR_TX_SET
#define UART_SCB__RX_CTRL CYREG_SCB0_RX_CTRL
#define UART_SCB__RX_FIFO_CTRL CYREG_SCB0_RX_FIFO_CTRL
#define UART_SCB__RX_FIFO_RD CYREG_SCB0_RX_FIFO_RD
#define UART_SCB__RX_FIFO_RD_SILENT CYREG_SCB0_RX_FIFO_RD_SILENT
#define UART_SCB__RX_FIFO_STATUS CYREG_SCB0_RX_FIFO_STATUS
#define UART_SCB__RX_MATCH CYREG_SCB0_RX_MATCH
#define UART_SCB__SPI_CTRL CYREG_SCB0_SPI_CTRL
#define UART_SCB__SPI_STATUS CYREG_SCB0_SPI_STATUS
#define UART_SCB__SS0_POSISTION 0u
#define UART_SCB__SS1_POSISTION 1u
#define UART_SCB__SS2_POSISTION 2u
#define UART_SCB__SS3_POSISTION 3u
#define UART_SCB__STATUS CYREG_SCB0_STATUS
#define UART_SCB__TX_CTRL CYREG_SCB0_TX_CTRL
#define UART_SCB__TX_FIFO_CTRL CYREG_SCB0_TX_FIFO_CTRL
#define UART_SCB__TX_FIFO_STATUS CYREG_SCB0_TX_FIFO_STATUS
#define UART_SCB__TX_FIFO_WR CYREG_SCB0_TX_FIFO_WR
#define UART_SCB__UART_CTRL CYREG_SCB0_UART_CTRL
#define UART_SCB__UART_FLOW_CTRL CYREG_SCB0_UART_FLOW_CTRL
#define UART_SCB__UART_RX_CTRL CYREG_SCB0_UART_RX_CTRL
#define UART_SCB__UART_RX_STATUS CYREG_SCB0_UART_RX_STATUS
#define UART_SCB__UART_TX_CTRL CYREG_SCB0_UART_TX_CTRL
#define UART_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL1
#define UART_SCBCLK__DIV_ID 0x00000040u
#define UART_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL0
#define UART_SCBCLK__PA_DIV_ID 0x000000FFu
#define UART_tx__0__DR CYREG_GPIO_PRT1_DR
#define UART_tx__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_tx__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_tx__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_tx__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define UART_tx__0__HSIOM_GPIO 0u
#define UART_tx__0__HSIOM_I2C 14u
#define UART_tx__0__HSIOM_I2C_SCL 14u
#define UART_tx__0__HSIOM_MASK 0x00F00000u
#define UART_tx__0__HSIOM_SHIFT 20u
#define UART_tx__0__HSIOM_SPI 15u
#define UART_tx__0__HSIOM_SPI_MISO 15u
#define UART_tx__0__HSIOM_UART 9u
#define UART_tx__0__HSIOM_UART_TX 9u
#define UART_tx__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__0__INTR CYREG_GPIO_PRT1_INTR
#define UART_tx__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_tx__0__MASK 0x20u
#define UART_tx__0__OUT_SEL CYREG_UDB_PA1_CFG10
#define UART_tx__0__OUT_SEL_SHIFT 10u
#define UART_tx__0__OUT_SEL_VAL -1u
#define UART_tx__0__PA__CFG0 CYREG_UDB_PA1_CFG0
#define UART_tx__0__PA__CFG1 CYREG_UDB_PA1_CFG1
#define UART_tx__0__PA__CFG10 CYREG_UDB_PA1_CFG10
#define UART_tx__0__PA__CFG11 CYREG_UDB_PA1_CFG11
#define UART_tx__0__PA__CFG12 CYREG_UDB_PA1_CFG12
#define UART_tx__0__PA__CFG13 CYREG_UDB_PA1_CFG13
#define UART_tx__0__PA__CFG14 CYREG_UDB_PA1_CFG14
#define UART_tx__0__PA__CFG2 CYREG_UDB_PA1_CFG2
#define UART_tx__0__PA__CFG3 CYREG_UDB_PA1_CFG3
#define UART_tx__0__PA__CFG4 CYREG_UDB_PA1_CFG4
#define UART_tx__0__PA__CFG5 CYREG_UDB_PA1_CFG5
#define UART_tx__0__PA__CFG6 CYREG_UDB_PA1_CFG6
#define UART_tx__0__PA__CFG7 CYREG_UDB_PA1_CFG7
#define UART_tx__0__PA__CFG8 CYREG_UDB_PA1_CFG8
#define UART_tx__0__PA__CFG9 CYREG_UDB_PA1_CFG9
#define UART_tx__0__PC CYREG_GPIO_PRT1_PC
#define UART_tx__0__PC2 CYREG_GPIO_PRT1_PC2
#define UART_tx__0__PORT 1u
#define UART_tx__0__PS CYREG_GPIO_PRT1_PS
#define UART_tx__0__SHIFT 5u
#define UART_tx__DR CYREG_GPIO_PRT1_DR
#define UART_tx__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_tx__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_tx__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_tx__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__INTR CYREG_GPIO_PRT1_INTR
#define UART_tx__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_tx__MASK 0x20u
#define UART_tx__PA__CFG0 CYREG_UDB_PA1_CFG0
#define UART_tx__PA__CFG1 CYREG_UDB_PA1_CFG1
#define UART_tx__PA__CFG10 CYREG_UDB_PA1_CFG10
#define UART_tx__PA__CFG11 CYREG_UDB_PA1_CFG11
#define UART_tx__PA__CFG12 CYREG_UDB_PA1_CFG12
#define UART_tx__PA__CFG13 CYREG_UDB_PA1_CFG13
#define UART_tx__PA__CFG14 CYREG_UDB_PA1_CFG14
#define UART_tx__PA__CFG2 CYREG_UDB_PA1_CFG2
#define UART_tx__PA__CFG3 CYREG_UDB_PA1_CFG3
#define UART_tx__PA__CFG4 CYREG_UDB_PA1_CFG4
#define UART_tx__PA__CFG5 CYREG_UDB_PA1_CFG5
#define UART_tx__PA__CFG6 CYREG_UDB_PA1_CFG6
#define UART_tx__PA__CFG7 CYREG_UDB_PA1_CFG7
#define UART_tx__PA__CFG8 CYREG_UDB_PA1_CFG8
#define UART_tx__PA__CFG9 CYREG_UDB_PA1_CFG9
#define UART_tx__PC CYREG_GPIO_PRT1_PC
#define UART_tx__PC2 CYREG_GPIO_PRT1_PC2
#define UART_tx__PORT 1u
#define UART_tx__PS CYREG_GPIO_PRT1_PS
#define UART_tx__SHIFT 5u

/* isr_1 */
#define isr_1__INTC_CLR_EN_REG CYREG_CM0_ICER
#define isr_1__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define isr_1__INTC_MASK 0x04u
#define isr_1__INTC_NUMBER 2u
#define isr_1__INTC_PRIOR_MASK 0xC00000u
#define isr_1__INTC_PRIOR_NUM 3u
#define isr_1__INTC_PRIOR_REG CYREG_CM0_IPR0
#define isr_1__INTC_SET_EN_REG CYREG_CM0_ISER
#define isr_1__INTC_SET_PD_REG CYREG_CM0_ISPR

/* Miscellaneous */
#define CY_PROJECT_NAME "Design01"
#define CY_VERSION "PSoC Creator  4.1 Update 1"
#define CYDEV_BANDGAP_VOLTAGE 1.024
#define CYDEV_BCLK__HFCLK__HZ 24000000U
#define CYDEV_BCLK__HFCLK__KHZ 24000U
#define CYDEV_BCLK__HFCLK__MHZ 24U
#define CYDEV_BCLK__SYSCLK__HZ 24000000U
#define CYDEV_BCLK__SYSCLK__KHZ 24000U
#define CYDEV_BCLK__SYSCLK__MHZ 24U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PSOC4A 16u
#define CYDEV_CHIP_DIE_PSOC5LP 2u
#define CYDEV_CHIP_DIE_PSOC5TM 3u
#define CYDEV_CHIP_DIE_TMA4 4u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_FM0P 5u
#define CYDEV_CHIP_FAMILY_FM3 6u
#define CYDEV_CHIP_FAMILY_FM4 7u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_PSOC6 4u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x0E34119Eu
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 16u
#define CYDEV_CHIP_MEMBER_4D 12u
#define CYDEV_CHIP_MEMBER_4E 6u
#define CYDEV_CHIP_MEMBER_4F 17u
#define CYDEV_CHIP_MEMBER_4G 4u
#define CYDEV_CHIP_MEMBER_4H 15u
#define CYDEV_CHIP_MEMBER_4I 21u
#define CYDEV_CHIP_MEMBER_4J 13u
#define CYDEV_CHIP_MEMBER_4K 14u
#define CYDEV_CHIP_MEMBER_4L 20u
#define CYDEV_CHIP_MEMBER_4M 19u
#define CYDEV_CHIP_MEMBER_4N 9u
#define CYDEV_CHIP_MEMBER_4O 7u
#define CYDEV_CHIP_MEMBER_4P 18u
#define CYDEV_CHIP_MEMBER_4Q 11u
#define CYDEV_CHIP_MEMBER_4R 8u
#define CYDEV_CHIP_MEMBER_4S 10u
#define CYDEV_CHIP_MEMBER_4U 5u
#define CYDEV_CHIP_MEMBER_5A 3u
#define CYDEV_CHIP_MEMBER_5B 2u
#define CYDEV_CHIP_MEMBER_6A 22u
#define CYDEV_CHIP_MEMBER_FM3 26u
#define CYDEV_CHIP_MEMBER_FM4 27u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u
#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4F
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u
#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u
#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u
#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4F_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_Disallowed
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DFT_SELECT_CLK0 10u
#define CYDEV_DFT_SELECT_CLK1 11u
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_IMO_TRIMMED_BY_USB 0u
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 1
#define CYDEV_VDDA 3.3
#define CYDEV_VDDA_MV 3300
#define CYDEV_VDDD 3.3
#define CYDEV_VDDD_MV 3300
#define CYDEV_VDDR 3.3
#define CYDEV_VDDR_MV 3300
#define CYDEV_WDT_GENERATE_ISR 1u
#define CYIPBLOCK_m0s8bless_VERSION 1
#define CYIPBLOCK_m0s8cpussv2_VERSION 1
#define CYIPBLOCK_m0s8csd_VERSION 1
#define CYIPBLOCK_m0s8ioss_VERSION 1
#define CYIPBLOCK_m0s8lcd_VERSION 2
#define CYIPBLOCK_m0s8lpcomp_VERSION 2
#define CYIPBLOCK_m0s8peri_VERSION 1
#define CYIPBLOCK_m0s8scb_VERSION 2
#define CYIPBLOCK_m0s8srssv2_VERSION 1
#define CYIPBLOCK_m0s8tcpwm_VERSION 2
#define CYIPBLOCK_m0s8udbif_VERSION 1
#define CYIPBLOCK_s8pass4al_VERSION 1
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
