Static Timing Analysis

Project : SCB_Flash_3.3
Build Time : 12/21/17 10:19:30
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 64.367 MHz
Clock_1 CyHFCLK 1.000 MHz 1.000 MHz 57.356 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 57.356 MHz 17.435 982.565
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,1) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/clock_0 \SPIM_1:BSPIM:state_0\/q 1.250
Route 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:tx_status_0\/main_2 5.889
macrocell2 U(0,0) 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/main_2 \SPIM_1:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 5.376
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM_1:BSPIM:RxStsReg\/status_6 65.407 MHz 15.289 984.711
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ \SPIM_1:BSPIM:sR8:Dp:u0\/clock \SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 5.280
Route 1 \SPIM_1:BSPIM:rx_status_4\ \SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM_1:BSPIM:rx_status_6\/main_5 2.777
macrocell4 U(0,1) 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/main_5 \SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/q \SPIM_1:BSPIM:RxStsReg\/status_6 2.312
statusicell2 U(0,1) 1 \SPIM_1:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:state_1\/q \SPIM_1:BSPIM:TxStsReg\/status_0 66.103 MHz 15.128 984.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \SPIM_1:BSPIM:state_1\ \SPIM_1:BSPIM:state_1\/clock_0 \SPIM_1:BSPIM:state_1\/q 1.250
Route 1 \SPIM_1:BSPIM:state_1\ \SPIM_1:BSPIM:state_1\/q \SPIM_1:BSPIM:tx_status_0\/main_1 3.582
macrocell2 U(0,0) 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/main_1 \SPIM_1:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 5.376
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:TxStsReg\/status_0 67.336 MHz 14.851 985.149
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/clock_0 \SPIM_1:BSPIM:state_2\/q 1.250
Route 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:tx_status_0\/main_0 3.305
macrocell2 U(0,0) 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/main_0 \SPIM_1:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM_1:BSPIM:tx_status_0\ \SPIM_1:BSPIM:tx_status_0\/q \SPIM_1:BSPIM:TxStsReg\/status_0 5.376
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:sR8:Dp:u0\/so_comb Net_61/main_4 68.069 MHz 14.691 985.309
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ \SPIM_1:BSPIM:sR8:Dp:u0\/clock \SPIM_1:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SPIM_1:BSPIM:mosi_from_dp\ \SPIM_1:BSPIM:sR8:Dp:u0\/so_comb Net_61/main_4 2.881
macrocell5 U(0,0) 1 Net_61 SETUP 3.510
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:TxStsReg\/status_3 69.541 MHz 14.380 985.620
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 2.110
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 3.992
macrocell1 U(0,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.358
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_1:BSPIM:state_2\/main_8 69.901 MHz 14.306 985.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ \SPIM_1:BSPIM:sR8:Dp:u0\/clock \SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb 5.280
Route 1 \SPIM_1:BSPIM:tx_status_1\ \SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_1:BSPIM:state_2\/main_8 5.516
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ SETUP 3.510
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 71.659 MHz 13.955 986.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 2.110
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 3.992
macrocell1 U(0,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.653
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 1.850
Clock Skew 0.000
\SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_1:BSPIM:state_1\/main_8 72.511 MHz 13.791 986.209
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ \SPIM_1:BSPIM:sR8:Dp:u0\/clock \SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb 5.280
Route 1 \SPIM_1:BSPIM:tx_status_1\ \SPIM_1:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_1:BSPIM:state_1\/main_8 5.001
macrocell7 U(0,0) 1 \SPIM_1:BSPIM:state_1\ SETUP 3.510
Clock Skew 0.000
\SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_2 72.516 MHz 13.790 986.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/clock_0 \SPIM_1:BSPIM:state_2\/q 1.250
Route 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_2 6.240
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 6.300
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 64.367 MHz 15.536 5.297
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P0[1] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 4.047
Route 1 Net_64 MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 4.709
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_63/q Net_63/main_3 3.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 Net_63 Net_63/clock_0 Net_63/q 1.250
macrocell9 U(1,0) 1 Net_63 Net_63/q Net_63/main_3 2.228
macrocell9 U(1,0) 1 Net_63 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,1) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/clock_0 \SPIM_1:BSPIM:load_cond\/q 1.250
macrocell10 U(0,1) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 2.294
macrocell10 U(0,1) 1 \SPIM_1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:state_2\/main_0 4.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/clock_0 \SPIM_1:BSPIM:state_2\/q 1.250
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/q \SPIM_1:BSPIM:state_2\/main_0 3.004
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_0 4.353
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,1) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/clock_0 \SPIM_1:BSPIM:state_0\/q 1.250
Route 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_0 3.103
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_1\/main_9 4.392
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_1\/main_9 3.142
macrocell7 U(0,0) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:ld_ident\/main_8 4.392
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
macrocell11 U(0,0) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:ld_ident\/main_8 3.142
macrocell11 U(0,0) 1 \SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q Net_61/main_10 4.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q Net_61/main_10 3.173
macrocell5 U(0,0) 1 Net_61 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_2\/main_9 4.424
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_2\/main_9 3.174
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_cond\/main_6 4.555
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 1.920
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_cond\/main_6 2.635
macrocell10 U(0,1) 1 \SPIM_1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_2\/q Net_61/main_1 4.555
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,0) 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/clock_0 \SPIM_1:BSPIM:state_2\/q 1.250
Route 1 \SPIM_1:BSPIM:state_2\ \SPIM_1:BSPIM:state_2\/q Net_61/main_1 3.305
macrocell5 U(0,0) 1 Net_61 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 7.449
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P0[1] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 2.740
Route 1 Net_64 MISO(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 4.709
datapathcell1 U(0,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_61/q MOSI(0)_PAD 22.379
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,0) 1 Net_61 Net_61/clock_0 Net_61/q 1.250
Route 1 Net_61 Net_61/q MOSI(0)/pin_input 6.034
iocell2 P0[0] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 15.095
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_62/q SCLK(0)_PAD 21.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,1) 1 Net_62 Net_62/clock_0 Net_62/q 1.250
Route 1 Net_62 Net_62/q SCLK(0)/pin_input 5.774
iocell3 P0[3] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 14.526
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyHFCLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_0 SS(0)_PAD 21.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_83 \Control_Reg_1:Sync:ctrl_reg\/control_0 SS(0)/pin_input 5.319
iocell4 P1[1] 1 SS(0) SS(0)/pin_input SS(0)/pad_out 14.005
Route 1 SS(0)_PAD SS(0)/pad_out SS(0)_PAD 0.000
Clock Clock path delay 0.000