Static Timing Analysis

Project : INS_AMP
Build Time : 06/10/13 17:31:08
Device : CY8C5568AXI-060
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClkIn(0)_PAD ClkIn(0)_PAD UNKNOWN UNKNOWN N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
+ Clock To Output Section
+ ClkIn(0)_PAD
Source Destination Delay (ns)
Net_837/q Xclk(0)_PAD 46.062
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(3,3) 1 Net_837 Net_837/clock_0 Net_837/q 1.250
Route 1 Net_837 Net_837/q Xclk(0)/pin_input 6.751
iocell10 P3[0] 1 Xclk(0) Xclk(0)/pin_input Xclk(0)/pad_out 16.911
Route 1 Xclk(0)_PAD Xclk(0)/pad_out Xclk(0)_PAD 0.000
Clock Clock path delay 21.150