Design Name D:/CAD_PROJECTS/AGILE_SOLUTIONS/FX3_DVK_TO_HSMC_BRIDGE/WORK/14_06_13_FINAL/FX3 DVK_TO_HSMC_BRIDGE.brd
Date Fri Jun 14 11:29:11 2013
Drawing Statistics:
Drawing Extents XL(-11712.5980) YL(-19055.1182) XU(38287.4020) YU(30944.8818)
Dimensions in mils with 4 decimal places
Package Symbols: Total(4) Mirrored(2) Embedded(0) Pins(392)
Mechanical Symbols: Total(0) Mirrored(0) Pins(0)
Format Symbols: Total(0)
DRC State: UP TO DATE
DRC Errors: 0
Short DRC: 0
Waived DRC: 0
Padstack Definitions: 156
Dynamic shapes: Total(7) Out_of_date(0)
Functions: Assigned(8) Unassigned(0) Total(8)
Connection Statistics:
Connections: W/Rats(151) No/Rats(0) Total(151)
Already Connected: W/Rats(151) No/Rats(0) Total(151)
Missing Connections: W/Rats(0) No/Rats(0) Total(0)
Dangling Connections (See logfile): 0
Connection Completion: W/Rats(100.00%) No/Rats(0.00%) Total(100.00%)
Manh Distance (inches): 158.6879
Etch Length (inches): W/Rats(173.61) No/Rats(0.00) Total(173.61)
Number of Vias: W/Rats(308) No/Rats(0) Total(308)
Vias per Connection: W/Rats(2.04) No/Rats(0.00)Total(2.04)
SMD pins with attached clines: 205
Layout Statistics:
Components: Placed(4) Unplaced(0) Total(4)
Nets: W/Rats(60) No/Rats(0) Total(60)
Pins: W/Rats(211) No/Rats(0) Unused(177) Unplaced(0) Total(388)
Equivalent ICs (1 pin = 1/14 EIC): 27
RatTs: 0
Router Keepin (in): (0.0000,0.0000) by (0.0000,0.0000)
Layout area (sq in): 0.00
Average ratlength (in): 1.2
Rat density (in/sq in): 0.000
Double-sided rat density (in/sq in): 0.000
Layout/Pin Density Statistics
Layer Layout Area
(sq in)		 Components Pins Layout Density
(sq in/EIC)		 Pin Density
(pins/sq in)
External(Double-Sided) 0.00 4 392 0.000 0.000
Embedded(0) 0.00 0 0 0.000 0.000
Design 0.00 4 392 0.000 0.000
Etch Layer Statistics:

Layer Clines/Carcs Shapes(voids) Rectangles Lines/Arcs Text Components(Pins)
TOP 81 6(76) 0 0 0 2(68)
L02_GND1 0 1(4) 0 0 0 0(0)
L03_SIG1 44 12(55) 0 0 0 0(0)
L04_SIG2 40 11(69) 0 0 0 0(0)
L05_PWR1 0 2(4) 0 0 0 0(0)
BOTTOM 202 6(64) 0 0 0 2(324)